Datasheet

Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0), with the exception of
the pins shown in the table below. A Power-On-Reset (POR) puts the pins back to their
default state.
Table 10-6. GPIO Pins With Non-Zero Reset Values
GPIOPCTLGPIOPURGPIOPDRGPIODENGPIOAFSELDefault StateGPIO Pins
0x11011JTAG/SWDPC[3:0]
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware signals including the GPIO pins that can function as
JTAG/SWD signals and the NMI signal. The commit control process must be followed
for these pins, even if they are programmed as alternate functions other than JTAG/SWD
or NMI; see “Commit Control” on page 783.
Note: If the device fails initialization during reset, the hardware toggles the TDO output
as an indication of failure. Thus, during board layout, designers should not
designate the TDO pin as a GPIO in sensitive applications where the possibility
of toggling could affect the design.
The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the
NMI pin and the four JTAG/SWD pins (see “Signal Tables” on page 2034 for pin numbers). These six
pins are the only GPIOs that are protected by the GPIOCR register. Because of this, the register
type for the corresponding GPIO Ports is RW.
The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception
of the NMI pin and the four JTAG/SWD pins (see “Signal Tables” on page 2034 for pin numbers). To
ensure that the JTAG and NMI pins are not accidentally programmed as GPIO pins, these pins
default to non-committable. Because of this, the default reset value of GPIOCR changes for the
corresponding ports.
Table 10-7. GPIO Register Map
See
page
DescriptionResetTypeNameOffset
790GPIO Data0x0000.0000RWGPIODATA0x000
791GPIO Direction0x0000.0000RWGPIODIR0x400
792GPIO Interrupt Sense0x0000.0000RWGPIOIS0x404
793GPIO Interrupt Both Edges0x0000.0000RWGPIOIBE0x408
794GPIO Interrupt Event0x0000.0000RWGPIOIEV0x40C
795GPIO Interrupt Mask0x0000.0000RWGPIOIM0x410
796GPIO Raw Interrupt Status0x0000.0000ROGPIORIS0x414
798GPIO Masked Interrupt Status0x0000.0000ROGPIOMIS0x418
800GPIO Interrupt Clear0x0000.0000W1CGPIOICR0x41C
801GPIO Alternate Function Select-RWGPIOAFSEL0x420
803GPIO 2-mA Drive Select0x0000.00FFRWGPIODR2R0x500
804GPIO 4-mA Drive Select0x0000.0000RWGPIODR4R0x504
787December 13, 2013
Texas Instruments-Advance Information
Tiva
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TM4C129XNCZAD Microcontroller