Datasheet

Table 10-5. GPIO Interrupt Configuration Example
Pin 2 Bit Value
a
Desired Interrupt
Event Trigger
Register
01234567
XX0XXXXX0=edge
1=level
GPIOIS
XX0XXXXX0=single edge
1=both edges
GPIOIBE
XX1XXXXX0=Low level, or falling
edge
1=High level, or rising
edge
GPIOIEV
001000000=masked
1=not masked
GPIOIM
a. X=Ignored (don’t care bit)
10.5 Register Map
Table 10-7 on page 787 lists the GPIO registers.
Important: The GPIO registers in this chapter are duplicated in each GPIO block; however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
cases, writing to unconnected bits has no effect, and reading unconnected bits returns
no meaningful data. See “Signal Description” on page 772 for the GPIOs included on
this device.
The offset listed is a hexadecimal increment to the register's address, relative to that GPIO port's
base address:
■ GPIO Port A (AHB): 0x4005.8000
■ GPIO Port B (AHB): 0x4005.9000
■ GPIO Port C (AHB): 0x4005.A000
■ GPIO Port D (AHB): 0x4005.B000
■ GPIO Port E (AHB): 0x4005.C000
■ GPIO Port F (AHB): 0x4005.D000
■ GPIO Port G (AHB): 0x4005.E000
■ GPIO Port H (AHB): 0x4005.F000
■ GPIO Port J (AHB): 0x4006.0000
■ GPIO Port K (AHB): 0x4006.1000
■ GPIO Port L (AHB): 0x4006.2000
■ GPIO Port M (AHB): 0x4006.3000
■ GPIO Port N (AHB): 0x4006.4000
■ GPIO Port P (AHB): 0x4006.5000
■ GPIO Port Q (AHB): 0x4006.6000
■ GPIO Port R (AHB): 0x4006.7000
■ GPIO Port S (AHB): 0x4006.8000
■ GPIO Port T (AHB): 0x4006.9000
Note that each GPIO module clock must be enabled before the registers can be programmed (see
page 398). There must be a delay of 3 system clocks after the GPIO module clock is enabled before
any GPIO module registers are accessed.
December 13, 2013786
Texas Instruments-Advance Information
General-Purpose Input/Outputs (GPIOs)