Datasheet

10.1 Signal Description
GPIO signals have alternate hardware functions. The following table lists the GPIO pins and their
analog and digital alternate functions. All GPIO signals are 5-V tolerant when configured as inputs
except for PB0 and PB1, which are limited to 3.6 V. The digital alternate hardware functions are
enabled by setting the appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL) and
GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL)
register to the numeric encoding shown in the table below. Analog signals in the table below are
also 3.3-V tolerant and are configured by clearing the DEN bit in the GPIO Digital Enable (GPIODEN)
register. The AINx analog signals have internal circuitry to protect them from voltages over V
DD
(up
to the maximum specified in Table 32-1 on page 2101), but analog performance specifications are
only guaranteed if the input signal swing at the I/O pad is kept inside the range 0 V < V
IN
< V
DD
.
Note that each pin must be programmed individually; no type of grouping is implied by the columns
in the table. Table entries that are shaded gray are the default values for the corresponding GPIO
pin.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0), with the exception of
the pins shown in the table below. A Power-On-Reset (POR) puts the pins back to their
default state.
Table 10-1. GPIO Pins With Non-Zero Reset Values
GPIOPCTLGPIOPURGPIOPDRGPIODENGPIOAFSELDefault StateGPIO Pins
0x11011JTAG/SWDPC[3:0]
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware signals including the GPIO pins that can function as
JTAG/SWD signals and the NMI signal. The commit control process must be followed
for these pins, even if they are programmed as alternate functions other than JTAG/SWD
or NMI; see “Commit Control” on page 783.
Note: If the device fails initialization during reset, the hardware toggles the TDO output
as an indication of failure. Thus, during board layout, designers should not
designate the TDO pin as a GPIO in sensitive applications where the possibility
of toggling could affect the design.
Table 10-2. GPIO Pins and Alternate Functions (212BGA)
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
b
Analog
or
Special
Function
a
PinIO
1514131187654321
-----
CAN0Rx
---
T0CCP0I2C9SCLU0Rx-V3PA0
-----
CAN0Tx
---
T0CCP1I2C9SDAU0Tx-W3PA1
SSI0Clk
--------
T1CCP0I2C8SCLU4Rx-T6PA2
SSI0Fss
--------
T1CCP1I2C8SDAU4Tx-U5PA3
SSI0XDAT0
--------
T2CCP0I2C7SCLU3Rx-V4PA4
SSI0XDAT1
--------
T2CCP1I2C7SDAU3Tx-W4PA5
EPI0S8EN0RXCKSSI0XDAT2
----
USB0EPEN
-
T3CCP0I2C6SCLU2Rx-V5PA6
EPI0S9
-
SSI0XDAT3USB0EPEN
---
USB0PFLT
-
T3CCP1I2C6SDAU2Tx-R7PA7
December 13, 2013772
Texas Instruments-Advance Information
General-Purpose Input/Outputs (GPIOs)