Datasheet

– Supports both transmitting and receiving data as either a master or a slave

– Supports simultaneous master and slave operation

■ Four I

C modes

– Master transmit

– Master receive

– Slave transmit

– Slave receive

■ Two 8-entry FIFOs for receive and transmit data

– FIFOs can be independently assigned to master or slave

■ Four transmission speeds:

– Standard (100 Kbps)

– Fast-mode (400 Kbps)

– Fast-mode plus (1 Mbps)

– High-speed mode (3.33 Mbps)

■ Glitch suppression

■ SMBus support through software

– Clock low timeout interrupt

– Dual slave address capability

– Quick command capability

■ Master and slave interrupt generation

– Master generates interrupts when a transmit or receive operation completes (or aborts due

to an error)

– Slave generates interrupts when data has been transferred or requested by a master or when

a START or STOP condition is detected

■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing

mode

■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)

– Separate channels for transmit and receive

– Ability to execute single data transfers or burst data transfers using the RX and TX FIFOs in

the I

December 13, 201374

Texas Instruments-Advance Information

Architectural Overview