Datasheet

11.4.2 SDRAM Mode ............................................................................................................. 853
11.4.3 Host Bus Mode ........................................................................................................... 857
11.4.4 General-Purpose Mode ............................................................................................... 878
11.5 Register Map .............................................................................................................. 885
11.6 Register Descriptions .................................................................................................. 887
12 Cyclical Redundancy Check (CRC) .................................................................... 977
12.1 Functional Description ................................................................................................. 977
12.1.1 CRC Support .............................................................................................................. 977
12.2 Initialization and Configuration ..................................................................................... 979
12.2.1 CRC Initialization and Configuration ............................................................................. 979
12.3 Register Map .............................................................................................................. 980
12.4 CRC Module Register Descriptions .............................................................................. 980
13 Advance Encryption Standard Accelerator (AES) ............................................ 986
13.1 AES Overview ............................................................................................................. 986
13.2 AES Functional Description .......................................................................................... 986
13.2.1 AES Block Diagram ..................................................................................................... 987
13.2.2 AES Algorithm ............................................................................................................ 990
13.2.3 AES Operating Modes ................................................................................................. 991
13.2.4 AES Software Reset .................................................................................................... 999
13.2.5 Power Management .................................................................................................... 999
13.2.6 Hardware Requests ..................................................................................................... 999
13.3 AES Performance Information .................................................................................... 1000
13.4 AES Module Programming Guide ............................................................................... 1002
13.4.1 AES Low - Level Programming Models ....................................................................... 1002
13.5 Register Map ............................................................................................................ 1007
13.6 AES Register Descriptions ......................................................................................... 1009
13.7 AES µDMA Interrupt Register Descriptions (CCM Offset) ............................................. 1031
14 Data Encryption Standard Accelerator (DES) ................................................. 1038
14.1 DES Functional Description ........................................................................................ 1038
14.2 DES Block Diagram ................................................................................................... 1039
14.2.1 µDMA Control ........................................................................................................... 1039
14.2.2 Interrupt Control ........................................................................................................ 1040
14.2.3 Register Interface ...................................................................................................... 1040
14.2.4 DES Engine .............................................................................................................. 1040
14.3 Software Reset ......................................................................................................... 1041
14.4 DES Supported Modes of Operation ........................................................................... 1041
14.4.1 ECB Feedback Mode ................................................................................................. 1041
14.5 DES Module Programming Guide -Low Level Programming Models ............................. 1043
14.5.1 Surrounding Modules Global Initialization .................................................................... 1043
14.5.2 Operational Modes Configuration ............................................................................... 1044
14.5.3 DES Events Servicing ................................................................................................ 1046
14.6 Register Map ............................................................................................................ 1047
14.7 DES Register Description .......................................................................................... 1048
14.8 DES µDMA Interrupt Register Descriptions (CCM Offset) ............................................. 1062
15 SHA/MD5 Accelerator ........................................................................................ 1067
15.1 SHA/MD5 Functional Description ................................................................................ 1067
15.1.1 SHA/MD5 Block Diagram ........................................................................................... 1067
7December 13, 2013
Texas Instruments-Advance Information
Tiva
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TM4C129XNCZAD Microcontroller