Datasheet

Register 11: Flash Peripheral Properties (FLASHPP), offset 0xFC0
Flash Peripheral Properties (FLASHPP)
Base 0x400F.D000
Offset 0xFC0
Type RO, reset 0xF014.01FF
16171819202122232425262728293031
MAINSSEESSreservedDFAFMMPFCreserved
ROROROROROROROROROROROROROROROROType
0010100000001110Reset
0123456789101112131415
SIZE
ROROROROROROROROROROROROROROROROType
1111111110000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31
Prefetch Buffer Mode
DescriptionValue
Single set of 2x256-bit buffers used.0
Two sets of 2x256-bit prefetch buffers are available to use and
may be enabled through the FLASHCONF register.
1
0x1ROPFC30
Flash Mirror Mode
DescriptionValue
Mirror Mode not available.0
Flash Mirror Mode is available to be enabled or disabled by user
through FLASHCONF register.
1
0x1ROFMM29
DMA Flash Access
Note: µDMA can only access flash in Run Mode (not available in
low power modes).
DescriptionValue
DMA cannot be used to access Flash0
DMA may access the Flash memory range specified by the
FLASHDMAST and FLASHDMASZ registers
1
0x1RODFA28
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved27:23
671December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller