Datasheet

Blocks
There are 96 blocks of 16 words each in the EEPROM. These are readable and writable as words.
Bytes and half-words can be read, and these accesses do not have to occur on a word boundary.
The entire word is read and any unneeded data is simply ignored. The EEPROM blocks are writable
only on a word basis. To write a byte, it is necessary to read the word value, modify the appropriate
byte, and write the word back.
Each block is addressable as an offset within the EEPROM, using a block select register. Each
word is offset addressable within the selected block.
The current block is selected by the EEPROM Current Block (EEBLOCK) register. The current
offset is selected and checked for validity by the EEPROM Current Offset (EEOFFSET) register.
The application may write the EEOFFSET register any time, and it is also automatically incremented
when the EEPROM Read-Write with Increment (EERDWRINC) register is accessed. However,
the EERDWRINC register does not increment the block number, but instead wraps within the block.
Blocks are individually protectable. Attempts to read from a block for which the application does not
have permission return 0xFFFF.FFFF. Attempts to write into a block for which the application does
not have permission results in an error in the EEPROM Done Status (EEDONE) register.
Timing Considerations
After enabling or resetting the EEPROM module, software must wait until the WORKING bit in the
EEDONE register is clear before accessing any EEPROM registers.
Note: Software must ensure there are no Flash memory writes or erases pending before performing
an EEPROM operation. When the FMC register reads as 0x0000.00000 and the WRBUF bit
of the FMC2 register is clear, there are no Flash memory writes or erases pending.
EEPROM operations must be completed before entering Sleep or Deep-Sleep mode. Ensure the
EEPROM operations have completed by checking the EEPROM Done Status (EEDONE) register
before issuing a WFI instruction to enter Sleep or Deep-Sleep.
Writes to words within a block are delayed by a variable amount of time. The application may use
an interrupt to be notified when the write is done, or alternatively poll for the done status in the
EEDONE register. The variability ranges from the write timing of the EEPROM to the erase timing
of EEPROM, where the erase timing is less than the write timing of most external EEPROMs.
Depending on the CPU frequency, the application must program the EEPROM Clock High Time
(EBCHT), EEPROM Bank Clock Edge (EBCE) and the EEPROM Wait States (EWS) in the Memory
Timing Parameter Register 0 for Main Flash and EEPROM (MEMTIM0) register at System Control
Module offset 0x0C0.
Table 8-4. MEMTIM0 Register Configuration versus Frequency
EEPROM Wait
States (EWS)
EEPROM Bank
Clock Edge
(EBCE)
EEPROM Bank Clock
High Time (EBCHT)
Time Period Range (t) in nsCPU Frequency range (f)
in MHz
0x010x062.516
0x100x262.5 > t ≥ 2516 < f ≤ 40
0x200x325 > t ≥ 16.6740 < f ≤60
0x300x416.67 > t ≥ 12.560< f ≤80
0x400x512.5 > t ≥ 1080 < f ≤100
0x500x610 > t ≥ 8.33100< f ≤120
December 13, 2013646
Texas Instruments-Advance Information
Internal Memory