Datasheet

address to the upper banks until the next swap. Figure 8-7 on page 639 depicts the configuration
necessary when executing Flash mirroring.
Note: After a mirror mode has been executed and the code locations have been swapped from
the upper memory banks to the lower, the application can continue to read from the lower
memory bank address locations. However, when erasing or programming the swapped
memory, the application must use the "real" upper memory address of the code before it
was swapped. For example, in Figure 8-7 on page 639, when the yellow highlighted location
0x00.3FE8 is swapped with 0x08.3FE8 the application's next read location is 0x00.3FEC.
However, if the application were to program or erase the next location it would need to write
or erase location 0x08.3FEC
Figure 8-7. Mirror Mode Function
0x07.FFFC 0x07.FFF8 0x07.FFF4 0x07.FFF0
0x00.3FFC 0x00.3FF8 0x00.3FF4 0x00.3FF0
0x00.401C 0x00.4018 0x00.4014 0x00.4010
0x00.001C 0x00.0018 0x00.0014 0x00.0010
8 KB Sector 0 Bank 1
8 KB Sector31-1 Bank 1
0x07.FFEC 0x07.FFE8 0x07.FFE4 0x07.FFE0
0x00.3FE80x00.3FEC 0x00.3FE4 0x00.3FE0
0x00.400C 0x00.4008 0x00.4004 0x00.4000
0x00.000C 0x00.0008 0x00.0004 0x00.0000
8 KB Sector 0 Bank 0
8 KB Sector31-1 Bank 0
Boot
Loader
Code
should
be
mirrored
in both
512 KB
Blocks
Boot
Loader
Code
should
be
mirrored
in both
512 KB
Blocks
Upper 512 KB Memory
Region This region contains
the mirrored application code.
Patches and updates can be
done in this upper 512 KB of
memory in the background
while the lower 512 KB is
being executed. It is
important to ensure that code
offsets remain the same as
the lower 512 KB memory
region so the memory swap is
seamless.
This entire region is swapped
when the FMME bit is set in
the FLASHCONF register.
Lower 512 KB
Memory Region
This region contains
the application code
being executed.
The application code should have a decision bit that
indicates whether the Flash regions are swapped or
not. If the FMME bit in the FLASHCONF register is set
to 1, then the swap happens immediately and the CPU
next memory fetch is from the swapped memory.
When the
FMME bit is
set the upper
512 KB
memory
region is
swapped
with the
lower 512 KB
region
0x0F.FFFC 0x0F.FFF8 0x0F.FFF4 0x0F.FFF0
0x08.3FFC 0x08.3FF8 0x08.3FF4 0x08.3FF0
0x08.401C 0x08.4018 0x08.4014 0x08.4010
0x08.001C 0x08.0018 0x08.0014 0x08.0010
8 KB Sector 0 Bank 3
8 KB Sector31-1 Bank 3
0x0F.FFEC 0x0F.FFE8 0x0F.FFE4 0x0F.FFE0
0x08.3FEC 0x08.3FE8 0x08.3FE4 0x08.3FE0
0x08.400C 0x08.4008 0x08.4004 0x08.4000
0x08.000C 0x08.0008 0x08.0004 0x08.0000
8 KB Sector 0 Bank 2
8 KB Sector31-1 Bank 2
8.2.3.4 Protected Flash Memory Registers
The user is provided execution protection through 16 pairs of 32-bit wide registers. The policy for
each protection form is controlled by individual bits (per policy per block) in the FMPPEn and
FMPREn registers.
■ Flash Memory Protection Program Enable (FMPPEn): In the Flash, 16-KB blocks can be
individually protected from being programed or erased. Because each bit of the FMPPE register
represents a 2-KB block, the application must clear all the bits in one byte to protect one 16-KB
block. Execute-only protection can only be programmed in 16-KB increments. For example, to
protect the first 16-KB block, bits [7:0] all need to be set to 0s. When bits in the FMPPEn register
are set, the corresponding block may be programmed (written) or erased. When bits are cleared,
the corresponding block may not be changed. When a block is protected by clearing bits in both
FMPPEn and FMPREn registers, execute-only protection can be achieved.
■ Flash Memory Protection Read Enable (FMPREn): If a bit is set in this register, the
corresponding block may be executed or read by software or debuggers. If a bits in this register
are cleared and the same block in the FMPREn register is cleared, the corresponding block may
639December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller