Datasheet

Register 33: Hibernation Clock Control (HIBCC), offset 0xFC8
This register enables alternate clock sources.
Note: This register is in the system clock domain. Writes to this register do not require waiting for
the WRC bit of the HIBCTL register to be set.
Hibernation Clock Control (HIBCC)
Base 0x400F.C000
Offset 0xFC8
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
SYSCLKEN
reserved
RWROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:1
RTCOSC to System Clock Enable
This bit RTCOSC clock to be sent to the system control for selection as
a possible system clock source. Default mode is disabled to support
low power modes.
DescriptionValue
RTCOSC is not available as a system clock source.0
RTCOSC is available for use as a system clock source.1
0x0RWSYSCLKEN0
629December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller