Datasheet

8.3 Register Map .............................................................................................................. 651
8.4 Internal Memory Register Descriptions (Internal Memory Control Offset) ......................... 653
8.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 679
8.6 Memory Register Descriptions (System Control Offset) .................................................. 696
9 Micro Direct Memory Access (μDMA) ................................................................ 707
9.1 Block Diagram ............................................................................................................ 708
9.2 Functional Description ................................................................................................. 708
9.2.1 Channel Assignments .................................................................................................. 709
9.2.2 Priority ........................................................................................................................ 710
9.2.3 Arbitration Size ............................................................................................................ 711
9.2.4 Request Types ............................................................................................................ 711
9.2.5 Channel Configuration ................................................................................................. 712
9.2.6 Transfer Modes ........................................................................................................... 714
9.2.7 Transfer Size and Increment ........................................................................................ 722
9.2.8 Peripheral Interface ..................................................................................................... 722
9.2.9 Software Request ........................................................................................................ 723
9.2.10 Interrupts and Errors .................................................................................................... 723
9.3 Initialization and Configuration ..................................................................................... 723
9.3.1 Module Initialization ..................................................................................................... 723
9.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 724
9.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 725
9.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 727
9.3.5 Configuring Channel Assignments ................................................................................ 730
9.4 Register Map .............................................................................................................. 730
9.5 μDMA Channel Control Structure ................................................................................. 731
9.6 μDMA Register Descriptions ........................................................................................ 738
10 General-Purpose Input/Outputs (GPIOs) ........................................................... 771
10.1 Signal Description ....................................................................................................... 772
10.2 Pad Capabilities .......................................................................................................... 777
10.3 Functional Description ................................................................................................. 777
10.3.1 Data Control ............................................................................................................... 779
10.3.2 Interrupt Control .......................................................................................................... 781
10.3.3 Mode Control .............................................................................................................. 782
10.3.4 Commit Control ........................................................................................................... 783
10.3.5 Pad Control ................................................................................................................. 783
10.3.6 Identification ............................................................................................................... 784
10.4 Initialization and Configuration ..................................................................................... 784
10.5 Register Map .............................................................................................................. 786
10.6 Register Descriptions .................................................................................................. 789
11 External Peripheral Interface (EPI) ..................................................................... 846
11.1 EPI Block Diagram ...................................................................................................... 847
11.2 Signal Description ....................................................................................................... 848
11.3 Functional Description ................................................................................................. 849
11.3.1 Master Access to EPI .................................................................................................. 850
11.3.2 Non-Blocking Reads .................................................................................................... 850
11.3.3 DMA Operation ........................................................................................................... 851
11.4 Initialization and Configuration ..................................................................................... 852
11.4.1 EPI Interface Options .................................................................................................. 853
December 13, 20136
Texas Instruments-Advance Information
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