Datasheet

DescriptionResetTypeNameBit/Field
Write Complete/Capable Raw Interrupt Status
DescriptionValue
The WRC bit in the HIBCTL has not been set.0
The WRC bit in the HIBCTL has been set.1
This bit is cleared by writing a 1 to the WC bit in the HIBIC register.
0ROWC4
External Wake-Up Raw Interrupt Status
Note that the WAKE signal source must be cleared by the application
after the interrupt has been registered.
DescriptionValue
The WAKE pin has not been asserted.0
The WAKE pin has been asserted.1
This bit is cleared by writing a 1 to the EXTW bit in the HIBIC register.
Note: The EXTW bit is set if the WAKE pin is asserted in any mode
of operation (run, sleep, deep-sleep).
0ROEXTW3
Low Battery Voltage Raw Interrupt Status
DescriptionValue
The battery voltage has not dropped below V
LOWBAT
.0
The battery voltage dropped below V
LOWBAT
.1
This bit is cleared by writing a 1 to the LOWBAT bit in the HIBIC register.
0ROLOWBAT2
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved1
RTC Alert 0 Raw Interrupt Status
DescriptionValue
No match0
If the RTC is enabled, t he value of the HIBRTCC register
matches the value in the HIBRTCM0 register and the value of
the RTCSSC field matches the RTCSSM field in the HIBRTCSS
register.
If the Calendar function is enabled, this interrupt status indicates
that one or more of the allowed fields in the HIBCAL0/1 register
matches in the HIBCALM0/1 register..
1
This bit is cleared by writing a 1 to the RTCALT0 bit in the HIBIC register.
0RORTCALT00
595December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller