Datasheet

are accessed. In addition, the CLK32EN bit in the HIBCTL register must be set before accessing
any other Hibernation module register.
Note: Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the WRC bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 565. The HIBIO register and bits RSTWK, PADIOWK and
WC of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL
register has been set may produce unexpected results.
Important: The Hibernation module registers are reset under two conditions:
1. Any type of system reset (if the RTCEN and the PINWEN bits in the HIBCTL register
are clear and the TPEN bit in the HIBTPCTL register is clear).
2. A cold POR occurs when both the V
DD
and V
BAT
supplies are removed.
Any other reset condition is ignored by the Hibernation module.
Note that the following registers are only accessed through privileged mode (see “System
Control” on page 230 for more details):
■ HIBTPCTL
■ HIBPTSTAT
■ HIBTPIO
■ HIBTPLOG
■ Upper eight words of memory (HIBDATA register 0x50 to 0x6F)
Table 7-3. Hibernation Module Register Map
See
page
DescriptionResetTypeNameOffset
584Hibernation RTC Counter0x0000.0000ROHIBRTCC0x000
585Hibernation RTC Match 00xFFFF.FFFFRWHIBRTCM00x004
586Hibernation RTC Load0x0000.0000WOHIBRTCLD0x00C
587Hibernation Control0x8000.2000RWHIBCTL0x010
592Hibernation Interrupt Mask0x0000.0000RWHIBIM0x014
594Hibernation Raw Interrupt Status0x0000.0000ROHIBRIS0x018
596Hibernation Masked Interrupt Status0x0000.0000ROHIBMIS0x01C
598Hibernation Interrupt Clear0x0000.0000RW1CHIBIC0x020
600Hibernation RTC Trim0x0000.7FFFRWHIBRTCT0x024
601Hibernation RTC Sub Seconds0x0000.0000RWHIBRTCSS0x028
December 13, 2013582
Texas Instruments-Advance Information
Hibernation Module