Datasheet

Register 195: Ethernet MAC Peripheral Ready (PREMAC), offset 0xA9C
The PREMAC register indicates whether the Ethernet Mocule module is ready to be accessed by
software following a change in status of power, Run mode clocking, or reset. A power change is
initiated if the corresponding PCEMAC bit is changed from 0 to 1. A Run mode clocking change is
initiated if the corresponding RCGCEMAC bit is changed. A reset change is initiated if the
corresponding SREMAC bit is changed from 0 to 1.
The PREMAC bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Ethernet MAC Peripheral Ready (PREMAC)
Base 0x400F.E000
Offset 0xA9C
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
R0reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:1
Ethernet MAC Module 0 Peripheral Ready
DescriptionValue
Ethernet MAC module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
0
Ethernet MAC module 0 is ready for access.1
0ROR00
5.6 Cryptographic System Control Register Description (CCM Offset)
This section lists and describes the system control registers for the CRC and Cryptographic (AES,
DES, SHA) Modules. Registers in this section are relative to the CCM base address of 0x4403.0000.
551December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller