Datasheet

Register 193: LCD Controller Peripheral Ready (PRLCD), offset 0xA90
The PRLCD register indicates whether the LCD Controller modules are ready to be accessed by
software following a change in status of power, Run mode clocking, or reset. A power change is
initiated if the corresponding PCLCD bit is changed from 0 to 1. A Run mode clocking change is
initiated if the corresponding RCGCLCD bit is changed. A reset change is initiated if the corresponding
SRLCD bit is changed from 0 to 1.
The PRLCD bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
LCD Controller Peripheral Ready (PRLCD)
Base 0x400F.E000
Offset 0xA90
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
R0reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:1
LCD Controller Module 0 Peripheral Ready
DescriptionValue
LCD Controller module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
0
LCD Controller module 0 is ready for access.1
0ROR00
549December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller