Datasheet

Revision History

The revision history table notes changes made between the indicated revisions of the

TM4C129XNCZAD data sheet.

Table 1. Revision History

DescriptionRevisionDate

■ Changed NDA (Non-Disclosure Agreement) footer to indicate NDA only applies to USB content.

■ In System Control chapter:

– Added sections "Optional Clock Output Signal (DIVSCLK)" and "Hardware System Service

Request".

– Removed some registers and bits:

• LDORDRIS bit from Raw Interrupt Status (RIS) register, LDORDIM bit from Interrupt Mask

Control (IMC) register, and LDORDMIS bit from Masked Interrupt Status and Clear (MISC)

• Deep Sleep Mode Memory Timing Register 0 for Main Flash and EEPROM

(DSMEMTIM0) register

• LDO Power Calibration (LDOPCAL) register

• LDO Sleep Power Control (LDOSPCTL) register

• LMINERR bit from Sleep/Deep-Sleep Power Mode Status (SDPMST) register

– Added LDOSME, TSPDE, PIOSCPDE, SRAMSM, SRAMLPM, FLASHLPM, and LDOSEQ bits in

SYSPROP register.

■ In Internal Memory chapter:

– Added subsections to "Flash Memory" section about Execute-Only Protection, Read-Only

Protection and Permanently Disabling Debug.

– Removed INVPL bit from EEPROM Done Status (EEDONE) register.

– Updated table "MEMTIM0 Register Configuration vs. Frequency" with lower wait states, and

improved performance values.

– Added EEPROM initialization code to "EEPROM Initialization and Configuration" section.

■ In the ADC chapter:

– Added section "Sample and Hold Window Control" and clarified section "Sample Phase Control".

– Clarified description of ADC Sample Phase Control (ADCSPC) register.

■ Updated Electrical Characteristics chapter based on characterization information received.

15638.2711December 2013

Initial release of NDA data sheet.15440.2698October 2013

53December 13, 2013

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TM4C129XNCZAD Microcontroller