Datasheet

Register 100: Ethernet PHY LED Configuration - MR37 (EPHYLEDCFG), address 0x025 ..................... 1836
LCD Controller ........................................................................................................................... 1847
Register 1: LCD PID Register Format (LCDPID), offset 0x000 ......................................................... 1870
Register 2: LCD Control (LCDCTL), offset 0x004 ............................................................................ 1871
Register 3: LCD LIDD Control (LCDLIDDCTL), offset 0x00C ............................................................ 1873
Register 4: LCD LIDD CS0 Configuration (LIDDCS0CFG), offset 0x010 ........................................... 1876
Register 5: LIDD CS0 Read/Write Address (LIDDCS0ADDR), offset 0x014 ...................................... 1877
Register 6: LIDD CS0 Data Read/Write Initiation (LIDDCS0DATA), offset 0x018 ............................... 1878
Register 7: LIDD CS1 Configuration (LIDDCS1CFG), offset 0x01C .................................................. 1879
Register 8: LIDD CS1 Address Read/Write Initiation (LIDDCS1ADDR), offset 0x020 ......................... 1880
Register 9: LIDD CS1 Data Read/Write Initiation (LIDDCS1DATA), offset 0x024 ............................... 1881
Register 10: LCD Raster Control (LCDRASTRCTL), offset 0x028 ...................................................... 1882
Register 11: LCD Raster Timing 0 (LCDRASTRTIM0), offset 0x02C ................................................... 1886
Register 12: LCD Raster Timing 1 (LCDRASTRTIM1), offset 0x030 ................................................... 1887
Register 13: LCD Raster Timing 2 (LCDRASTRTIM2), offset 0x034 ................................................... 1888
Register 14: LCD Raster Subpanel Display 1 (LCDRASTRSUBP1), offset 0x038 ................................ 1891
Register 15: LCD Raster Subpanel Display 2 (LCDRASTRSUBP2), offset 0x03C ............................... 1892
Register 16: LCD DMA Control (LCDDMACTL), offset 0x040 ............................................................. 1893
Register 17: LCD DMA Frame Buffer 0 Base Address (LCDDMABAFB0), offset 0x044 ....................... 1895
Register 18: LCD DMA Frame Buffer 0 Ceiling Address (LCDDMACAFB0), offset 0x048 .................... 1896
Register 19: LCD DMA Frame Buffer 1 Base Address (LCDDMABAFB1), offset 0x04C ....................... 1897
Register 20: LCD DMA Frame Buffer 1 Ceiling Address (LCDDMACAFB1), offset 0x050 .................... 1898
Register 21: LCD System Configuration Register (LCDSYSCFG), offset 0x054 .................................. 1899
Register 22: LCD Interrupt Raw Status and Set Register (LCDRISSET), offset 0x058 ......................... 1901
Register 23: LCD Interrupt Status and Clear (LCDMISCLR), offset 0x05C .......................................... 1904
Register 24: LCD Interrupt Mask (LCDIM), offset 0x060 .................................................................... 1907
Register 25: LCD Interrupt Enable Clear (LCDIENC), offset 0x064 ..................................................... 1910
Register 26: LCD Clock Enable (LCDCLKEN), offset 0x06C .............................................................. 1913
Register 27: LCD Clock Resets (LCDCLKRESET), offset 0x070 ........................................................ 1914
Analog Comparators ................................................................................................................. 1915
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 ................................ 1922
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ..................................... 1923
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ....................................... 1924
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ..................... 1925
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ................................................... 1926
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ................................................... 1926
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x060 ................................................... 1926
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x024 ................................................... 1927
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x044 ................................................... 1927
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x064 ................................................... 1927
Register 11: Analog Comparator Peripheral Properties (ACMPPP), offset 0xFC0 ................................ 1929
Pulse Width Modulator (PWM) .................................................................................................. 1931
Register 1: PWM Master Control (PWMCTL), offset 0x000 .............................................................. 1945
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ......................................................... 1947
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 ........................................................ 1948
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ..................................................... 1950
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 .............................................................. 1952
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ......................................................... 1954
December 13, 201350
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