Datasheet

Register 151: LCD Controller Deep-Sleep Mode Clock Gating Control
(DCGCLCD), offset 0x890
The DCGCLCD register provides software the capability to enable and disable the LCD Controller
module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock
is disabled to save power.
Important: This register should be used to control the clocking for the LCD Controller module.
LCD Controller Deep-Sleep Mode Clock Gating Control (DCGCLCD)
Base 0x400F.E000
Offset 0x890
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
D0reserved
RWROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:1
LCD Controller Module 0 Deep-Sleep Mode Clock Gating Control
DescriptionValue
LCD Controller module 0 is disabled in deep-sleep mode.0
Enable and provide a clock to LCD Controller module 0 in
deep-sleep mode.
1
0RWD00
December 13, 2013470
Texas Instruments-Advance Information
System Control