TEXAS INSTRUMENTS PCB design board : Datasheet : Page 46

Register 20: QSSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ........................................ 1419

Register 21: QSSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ........................................... 1420

Register 22: QSSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ........................................... 1421

Register 23: QSSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ........................................... 1422

Register 24: QSSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC .......................................... 1423

Inter-Integrated Circuit (I

2

C) Interface ...................................................................................... 1424

Register 1: I

2

C Master Slave Address (I2CMSA), offset 0x000 ......................................................... 1451

Register 2: I

2

C Master Control/Status (I2CMCS), offset 0x004 ......................................................... 1452

Register 3: I

2

C Master Data (I2CMDR), offset 0x008 ....................................................................... 1461

Register 4: I

2

C Master Timer Period (I2CMTPR), offset 0x00C ......................................................... 1462

Register 5: I

2

C Master Interrupt Mask (I2CMIMR), offset 0x010 ....................................................... 1464

Register 6: I

2

C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ............................................... 1467

Register 7: I

2

C Master Masked Interrupt Status (I2CMMIS), offset 0x018 .......................................... 1470

Register 8: I

2

C Master Interrupt Clear (I2CMICR), offset 0x01C ....................................................... 1473

Register 9: I

2

C Master Configuration (I2CMCR), offset 0x020 .......................................................... 1475

Register 10: I

2

C Master Clock Low Timeout Count (I2CMCLKOCNT), offset 0x024 ............................. 1476

Register 11: I

2

C Master Bus Monitor (I2CMBMON), offset 0x02C ....................................................... 1477

Register 12: I

2

C Master Burst Length (I2CMBLEN), offset 0x030 ....................................................... 1478

Register 13: I

2

C Master Burst Count (I2CMBCNT), offset 0x034 ........................................................ 1479

Register 14: I

2

C Slave Own Address (I2CSOAR), offset 0x800 .......................................................... 1480

Register 15: I

2

C Slave Control/Status (I2CSCSR), offset 0x804 ......................................................... 1481

Register 16: I

2

C Slave Data (I2CSDR), offset 0x808 ......................................................................... 1484

Register 17: I

2

C Slave Interrupt Mask (I2CSIMR), offset 0x80C ......................................................... 1485

Register 18: I

2

C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................. 1487

Register 19: I

2

C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 ............................................ 1490

Register 20: I

2

C Slave Interrupt Clear (I2CSICR), offset 0x818 .......................................................... 1493

Register 21: I

2

C Slave Own Address 2 (I2CSOAR2), offset 0x81C ..................................................... 1495

Register 22: I

2

C Slave ACK Control (I2CSACKCTL), offset 0x820 ...................................................... 1496

Register 23: I

2

C FIFO Data (I2CFIFODATA), offset 0xF00 ................................................................. 1497

Register 24: I

2

C FIFO Control (I2CFIFOCTL), offset 0xF04 ............................................................... 1499

Register 25: I

2

C FIFO Status (I2CFIFOSTATUS), offset 0xF08 .......................................................... 1501

Register 26: I

2

C Peripheral Properties (I2CPP), offset 0xFC0 ............................................................ 1503

Register 27: I

2

C Peripheral Configuration (I2CPC), offset 0xFC4 ....................................................... 1504

1-Wire Master Module ................................................................................................................ 1505

Register 1: 1-Wire Control and Status (ONEWIRECS), offset 0x000 ................................................. 1517

Register 2: 1-Wire Timing Override (ONEWIRETIM), offset 0x004 .................................................... 1521

Register 3: 1-Wire Data Write (ONEWIREDATW), offset 0x008 ........................................................ 1522

Register 4: 1-Wire Data Read (ONEWIREDATR), offset 0x00C ........................................................ 1523

Register 5: 1-Wire Interrupt Mask (ONEWIREIM), offset 0x100 ........................................................ 1524

Register 6: 1-Wire Raw Interrupt Status (ONEWIRERIS), offset 0x104 ............................................. 1526

Register 7: 1-Wire Masked Interrupt Status (ONEWIREMIS), offset 0x108 ........................................ 1528

Register 8: 1-Wire Interrupt Clear (ONEWIREICR), offset 0x10C ..................................................... 1530

Register 9: 1-Wire µDMA Control (ONEWIREDMA), offset 0x120 ..................................................... 1531

Register 10: 1-Wire Peripheral Properties (ONEWIREPP), offset 0xFC0 ............................................ 1533

Controller Area Network (CAN) Module ................................................................................... 1534

Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................ 1556

December 13, 201346

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