Datasheet

Register 135: General-Purpose Input/Output Deep-Sleep Mode Clock Gating
Control (DCGCGPIO), offset 0x808
The DCGCGPIO register provides software the capability to enable and disable GPIO modules in
deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power.
Important: This register should be used to control the clocking for the GPIO modules.
General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO)
Base 0x400F.E000
Offset 0x808
Type RW, reset 0x0000.0000
16171819202122232425262728293031
D16D17reserved
RWRWROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:18
GPIO Port T Deep-Sleep Mode Clock Gating Control
DescriptionValue
GPIO Port T is disabled in deep-sleep mode.0
Enable and provide a clock to GPIO Port T in deep-sleep mode.1
0RWD1717
GPIO Port S Deep-Sleep Mode Clock Gating Control
DescriptionValue
GPIO Port S is disabled in deep-sleep mode.0
Enable and provide a clock to GPIO Port S in deep-sleep mode.1
0RWD1616
GPIO Port R Deep-Sleep Mode Clock Gating Control
DescriptionValue
GPIO Port R is disabled in deep-sleep mode.0
Enable and provide a clock to GPIO Port R in deep-sleep mode.1
0RWD1515
GPIO Port Q Deep-Sleep Mode Clock Gating Control
DescriptionValue
GPIO Port Q is disabled in deep-sleep mode.0
Enable and provide a clock to GPIO Port Q in deep-sleep mode.1
0RWD1414
December 13, 2013450
Texas Instruments-Advance Information
System Control