Datasheet

Register 3: UART Flag (UARTFR), offset 0x018 .............................................................................. 1329
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................ 1332
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 .......................................... 1333
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ..................................... 1334
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................. 1335
Register 8: UART Control (UARTCTL), offset 0x030 ........................................................................ 1337
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 .......................................... 1341
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................ 1343
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C .................................................... 1347
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ............................................... 1351
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 .............................................................. 1355
Register 14: UART DMA Control (UARTDMACTL), offset 0x048 ........................................................ 1357
Register 15: UART 9-Bit Self Address (UART9BITADDR), offset 0x0A4 ............................................. 1358
Register 16: UART 9-Bit Self Address Mask (UART9BITAMASK), offset 0x0A8 .................................. 1359
Register 17: UART Peripheral Properties (UARTPP), offset 0xFC0 .................................................... 1360
Register 18: UART Clock Configuration (UARTCC), offset 0xFC8 ...................................................... 1362
Register 19: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ................................... 1363
Register 20: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ................................... 1364
Register 21: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ................................... 1365
Register 22: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ................................... 1366
Register 23: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 .................................... 1367
Register 24: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 .................................... 1368
Register 25: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 .................................... 1369
Register 26: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ................................... 1370
Register 27: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ...................................... 1371
Register 28: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ...................................... 1372
Register 29: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ...................................... 1373
Register 30: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ...................................... 1374
Quad Synchronous Serial Interface (QSSI) ............................................................................. 1375
Register 1: QSSI Control 0 (SSICR0), offset 0x000 ......................................................................... 1393
Register 2: QSSI Control 1 (SSICR1), offset 0x004 ......................................................................... 1395
Register 3: QSSI Data (SSIDR), offset 0x008 ................................................................................. 1398
Register 4: QSSI Status (SSISR), offset 0x00C ............................................................................... 1399
Register 5: QSSI Clock Prescale (SSICPSR), offset 0x010 .............................................................. 1401
Register 6: QSSI Interrupt Mask (SSIIM), offset 0x014 .................................................................... 1402
Register 7: QSSI Raw Interrupt Status (SSIRIS), offset 0x018 ......................................................... 1404
Register 8: QSSI Masked Interrupt Status (SSIMIS), offset 0x01C ................................................... 1406
Register 9: QSSI Interrupt Clear (SSIICR), offset 0x020 .................................................................. 1408
Register 10: QSSI DMA Control (SSIDMACTL), offset 0x024 ............................................................. 1409
Register 11: QSSI Peripheral Properties (SSIPP), offset 0xFC0 ......................................................... 1410
Register 12: QSSI Clock Configuration (SSICC), offset 0xFC8 ........................................................... 1411
Register 13: QSSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ........................................ 1412
Register 14: QSSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ........................................ 1413
Register 15: QSSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ........................................ 1414
Register 16: QSSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ........................................ 1415
Register 17: QSSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ........................................ 1416
Register 18: QSSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ........................................ 1417
Register 19: QSSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ........................................ 1418
45December 13, 2013
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TM4C129XNCZAD Microcontroller