Datasheet
Register 26: ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 ............. 1271
Register 27: ADC Sample Sequence Extended Input Multiplexer Select 0 (ADCSSEMUX0), offset
0x058 .......................................................................................................................... 1273
Register 28: ADC Sample Sequence 0 Sample and Hold Time (ADCSSTSH0), offset 0x05C .............. 1275
Register 29: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............. 1277
Register 30: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............. 1277
Register 31: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ...................................... 1278
Register 32: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ...................................... 1278
Register 33: ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 .................................... 1282
Register 34: ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ................................... 1282
Register 35: ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 ............. 1283
Register 36: ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 ............ 1283
Register 37: ADC Sample Sequence Extended Input Multiplexer Select 1 (ADCSSEMUX1), offset
0x078 .......................................................................................................................... 1285
Register 38: ADC Sample Sequence Extended Input Multiplexer Select 2 (ADCSSEMUX2), offset 0x098
.................................................................................................................................... 1285
Register 39: ADC Sample Sequence 1 Sample and Hold Time (ADCSSTSH1), offset 0x07C .............. 1287
Register 40: ADC Sample Sequence 2 Sample and Hold Time (ADCSSTSH2), offset 0x09C .............. 1287
Register 41: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............. 1289
Register 42: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ...................................... 1290
Register 43: ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 .................................... 1292
Register 44: ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 ............ 1293
Register 45: ADC Sample Sequence Extended Input Multiplexer Select 3 (ADCSSEMUX3), offset
0x0B8 ......................................................................................................................... 1294
Register 46: ADC Sample Sequence 3 Sample and Hold Time (ADCSSTSH3), offset 0x0BC .............. 1295
Register 47: ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ................... 1296
Register 48: ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ..................................... 1301
Register 49: ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ..................................... 1301
Register 50: ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ..................................... 1301
Register 51: ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C .................................... 1301
Register 52: ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ..................................... 1301
Register 53: ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ..................................... 1301
Register 54: ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ..................................... 1301
Register 55: ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C .................................... 1301
Register 56: ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ..................................... 1304
Register 57: ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ..................................... 1304
Register 58: ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ..................................... 1304
Register 59: ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C .................................... 1304
Register 60: ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ..................................... 1304
Register 61: ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ..................................... 1304
Register 62: ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ..................................... 1304
Register 63: ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C .................................... 1304
Register 64: ADC Peripheral Properties (ADCPP), offset 0xFC0 ........................................................ 1305
Register 65: ADC Peripheral Configuration (ADCPC), offset 0xFC4 ................................................... 1307
Register 66: ADC Clock Configuration (ADCCC), offset 0xFC8 .......................................................... 1308
Universal Asynchronous Receivers/Transmitters (UARTs) ................................................... 1309
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................. 1324
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ......................... 1326
December 13, 201344
Texas Instruments-Advance Information
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