Datasheet
Register 28: GPTM Clock Configuration (GPTMCC), offset 0xFC8 ..................................................... 1174
Watchdog Timers ....................................................................................................................... 1175
Register 1: Watchdog Load (WDTLOAD), offset 0x000 .................................................................... 1179
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................. 1180
Register 3: Watchdog Control (WDTCTL), offset 0x008 ................................................................... 1181
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C ......................................................... 1183
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ................................................ 1184
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ........................................... 1185
Register 7: Watchdog Test (WDTTEST), offset 0x418 ...................................................................... 1186
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 .................................................................... 1187
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ............................... 1188
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ............................... 1189
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ............................... 1190
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC .............................. 1191
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ............................... 1192
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ............................... 1193
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ............................... 1194
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ............................... 1195
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................. 1196
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................. 1197
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................. 1198
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ................................ 1199
Analog-to-Digital Converter (ADC) ........................................................................................... 1200
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ........................................... 1225
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ......................................................... 1227
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 .................................................................... 1230
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C ................................................ 1233
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 .......................................................... 1237
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ............................................... 1239
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ......................................................... 1244
Register 8: ADC Trigger Source Select (ADCTSSEL), offset 0x01C ................................................. 1245
Register 9: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ........................................... 1247
Register 10: ADC Sample Phase Control (ADCSPC), offset 0x024 .................................................... 1249
Register 11: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ............................... 1251
Register 12: ADC Sample Averaging Control (ADCSAC), offset 0x030 ............................................... 1253
Register 13: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ............... 1254
Register 14: ADC Control (ADCCTL), offset 0x038 ............................................................................ 1256
Register 15: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............. 1257
Register 16: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ...................................... 1259
Register 17: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 .............................. 1266
Register 18: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 .............................. 1266
Register 19: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 .............................. 1266
Register 20: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................. 1266
Register 21: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ........................... 1267
Register 22: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ........................... 1267
Register 23: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C .......................... 1267
Register 24: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC .......................... 1267
Register 25: ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 .................................... 1269
43December 13, 2013
Texas Instruments-Advance Information
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TM4C129XNCZAD Microcontroller