Datasheet

Register 25: SHA Data 5 Input (SHA_DATA_5_IN), offset 0x094 ........................................................ 1090
Register 26: SHA Data 6 Input (SHA_DATA_6_IN), offset 0x098 ........................................................ 1090
Register 27: SHA Data 7 Input (SHA_DATA_7_IN), offset 0x09C ....................................................... 1090
Register 28: SHA Data 8 Input (SHA_DATA_8_IN), offset 0x0A0 ....................................................... 1090
Register 29: SHA Data 9 Input (SHA_DATA_9_IN), offset 0x0A4 ....................................................... 1090
Register 30: SHA Data 10 Input (SHA_DATA_10_IN), offset 0x0A8 .................................................... 1090
Register 31: SHA Data 11 Input (SHA_DATA_11_IN), offset 0x0AC .................................................... 1090
Register 32: SHA Data 12 Input (SHA_DATA_12_IN), offset 0x0B0 .................................................... 1090
Register 33: SHA Data 13 Input (SHA_DATA_13_IN), offset 0x0B4 .................................................... 1090
Register 34: SHA Data 14 Input (SHA_DATA_14_IN), offset 0x0B8 .................................................... 1090
Register 35: SHA Data 15 Input (SHA_DATA_15_IN), offset 0x0BC ................................................... 1090
Register 36: SHA Revision (SHA_REVISION), offset 0x100 .............................................................. 1091
Register 37: SHA System Configuration (SHA_SYSCONFIG), offset 0x110 ........................................ 1092
Register 38: SHA System Status (SHA_SYSSTATUS), offset 0x114 ................................................... 1094
Register 39: SHA Interrupt Status (SHA_IRQSTATUS), offset 0x118 .................................................. 1095
Register 40: SHA Interrupt Enable (SHA_IRQENABLE), offset 0x11C ................................................ 1096
Register 41: SHA DMA Interrupt Mask (SHA_DMAIM), offset 0x010 .................................................. 1098
Register 42: SHA DMA Raw Interrupt Status (SHA_DMARIS), offset 0x014 ....................................... 1099
Register 43: SHA DMA Masked Interrupt Status (SHA_DMAMIS), offset 0x018 .................................. 1100
Register 44: SHA DMA Interrupt Clear (SHA_DMAIC), offset 0x01C .................................................. 1101
General-Purpose Timers ........................................................................................................... 1102
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 ............................................................. 1124
Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004 ......................................................... 1125
Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008 ......................................................... 1129
Register 4: GPTM Control (GPTMCTL), offset 0x00C ...................................................................... 1133
Register 5: GPTM Synchronize (GPTMSYNC), offset 0x010 ............................................................ 1137
Register 6: GPTM Interrupt Mask (GPTMIMR), offset 0x018 ............................................................ 1140
Register 7: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ................................................... 1143
Register 8: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 .............................................. 1146
Register 9: GPTM Interrupt Clear (GPTMICR), offset 0x024 ............................................................ 1149
Register 10: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 .............................................. 1151
Register 11: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C .............................................. 1152
Register 12: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 ................................................ 1153
Register 13: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................ 1154
Register 14: GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ..................................................... 1155
Register 15: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ..................................................... 1156
Register 16: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ......................................... 1157
Register 17: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ......................................... 1158
Register 18: GPTM Timer A (GPTMTAR), offset 0x048 ..................................................................... 1159
Register 19: GPTM Timer B (GPTMTBR), offset 0x04C ..................................................................... 1160
Register 20: GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................. 1161
Register 21: GPTM Timer B Value (GPTMTBV), offset 0x054 ............................................................ 1162
Register 22: GPTM RTC Predivide (GPTMRTCPD), offset 0x058 ...................................................... 1163
Register 23: GPTM Timer A Prescale Snapshot (GPTMTAPS), offset 0x05C ...................................... 1164
Register 24: GPTM Timer B Prescale Snapshot (GPTMTBPS), offset 0x060 ...................................... 1165
Register 25: GPTM DMA Event (GPTMDMAEV), offset 0x06C .......................................................... 1166
Register 26: GPTM ADC Event (GPTMADCEV), offset 0x070 ........................................................... 1169
Register 27: GPTM Peripheral Properties (GPTMPP), offset 0xFC0 ................................................... 1172
December 13, 201342
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