Datasheet

Data Encryption Standard Accelerator (DES) ......................................................................... 1038
Register 1: DES Key 3 LSW for 192-Bit Key (DES_KEY3_L), offset 0x000 ....................................... 1049
Register 2: DES Key 3 MSW for 192-Bit Key (DES_KEY3_H), offset 0x004 ...................................... 1049
Register 3: DES Key 2 LSW for 128-Bit Key (DES_KEY2_L), offset 0x008 ....................................... 1049
Register 4: DES Key 2 MSW for 128-Bit Key (DES_KEY2_H), offset 0x00C ..................................... 1049
Register 5: DES Key 1 LSW for 64-Bit Key (DES_KEY1_L), offset 0x010 ......................................... 1049
Register 6: DES Key 1 MSW for 64-Bit Key (DES_KEY1_H), offset 0x014 ........................................ 1049
Register 7: DES Initialization Vector (DES_IV_L), offset 0x018 ........................................................ 1050
Register 8: DES Initialization Vector (DES_IV_H), offset 0x01C ....................................................... 1051
Register 9: DES Control (DES_CTRL), offset 0x020 ........................................................................ 1052
Register 10: DES Cryptographic Data Length (DES_LENGTH), offset 0x024 ...................................... 1053
Register 11: DES LSW Data RW (DES_DATA_L), offset 0x028 ......................................................... 1054
Register 12: DES MSW Data RW (DES_DATA_H), offset 0x02C ....................................................... 1055
Register 13: DES Revision Number (DES_REVISION), offset 0x030 .................................................. 1056
Register 14: DES System Configuration (DES_SYSCONFIG), offset 0x034 ........................................ 1057
Register 15: DES System Status (DES_SYSSTATUS), offset 0x038 .................................................. 1059
Register 16: DES Interrupt Status (DES_IRQSTATUS), offset 0x03C ................................................. 1060
Register 17: DES Interrupt Enable (DES_IRQENABLE), offset 0x040 ................................................ 1061
Register 18: DES Dirty Bits (DES_DIRTYBITS), offset 0x044 ............................................................ 1062
Register 19: DES DMA Interrupt Mask (DES_DMAIM), offset 0x030 .................................................. 1063
Register 20: DES DMA Raw Interrupt Status (DES_DMARIS), offset 0x034 ....................................... 1064
Register 21: DES DMA Masked Interrupt Status (DES_DMAMIS), offset 0x038 .................................. 1065
Register 22: DES DMA Interrupt Clear (DES_DMAIC), offset 0x03C .................................................. 1066
SHA/MD5 Accelerator ................................................................................................................ 1067
Register 1: SHA Outer Digest A (SHA_ODIGEST_A), offset 0x000 .................................................. 1085
Register 2: SHA Outer Digest B (SHA_ODIGEST_B), offset 0x004 .................................................. 1085
Register 3: SHA Outer Digest C (SHA_ODIGEST_C), offset 0x008 .................................................. 1085
Register 4: SHA Outer Digest D (SHA_ODIGEST_D), offset 0x00C ................................................. 1085
Register 5: SHA Outer Digest E (SHA_ODIGEST_E), offset 0x010 .................................................. 1085
Register 6: SHA Outer Digest F (SHA_ODIGEST_F), offset 0x014 ................................................... 1085
Register 7: SHA Outer Digest G (SHA_ODIGEST_G), offset 0x018 ................................................. 1085
Register 8: SHA Outer Digest H (SHA_ODIGEST_H), offset 0x01C ................................................. 1085
Register 9: SHA Inner Digest A (SHA_IDIGEST_A), offset 0x020 ..................................................... 1085
Register 10: SHA Inner Digest B (SHA_IDIGEST_B), offset 0x024 ..................................................... 1085
Register 11: SHA Inner Digest C (SHA_IDIGEST_C), offset 0x028 .................................................... 1085
Register 12: SHA Inner Digest D (SHA_IDIGEST_D), offset 0x02C .................................................... 1085
Register 13: SHA Inner Digest E (SHA_IDIGEST_E), offset 0x030 ..................................................... 1085
Register 14: SHA Inner Digest F (SHA_IDIGEST_F), offset 0x034 ..................................................... 1085
Register 15: SHA Inner Digest G (SHA_IDIGEST_G), offset 0x038 .................................................... 1085
Register 16: SHA Inner Digest H (SHA_IDIGEST_H), offset 0x03C .................................................... 1085
Register 17: SHA Digest Count (SHA_DIGEST_COUNT), offset 0x040 .............................................. 1086
Register 18: SHA Mode (SHA_MODE), offset 0x044 ......................................................................... 1087
Register 19: SHA Length (SHA_LENGTH), offset 0x048 ................................................................... 1089
Register 20: SHA Data 0 Input (SHA_DATA_0_IN), offset 0x080 ........................................................ 1090
Register 21: SHA Data 1 Input (SHA_DATA_1_IN), offset 0x084 ........................................................ 1090
Register 22: SHA Data 2 Input (SHA_DATA_2_IN), offset 0x088 ........................................................ 1090
Register 23: SHA Data 3 Input (SHA_DATA_3_IN), offset 0x08C ....................................................... 1090
Register 24: SHA Data 4 Input (SHA_DATA_4_IN), offset 0x090 ........................................................ 1090
41December 13, 2013
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TM4C129XNCZAD Microcontroller