Datasheet
Register 56: Flash Memory Protection Program Enable 4 (FMPPE4), offset 0x410 ............................... 700
Register 57: Flash Memory Protection Program Enable 5 (FMPPE5), offset 0x414 ............................... 700
Register 58: Flash Memory Protection Program Enable 6 (FMPPE6), offset 0x418 ............................... 700
Register 59: Flash Memory Protection Program Enable 7 (FMPPE7), offset 0x41C ............................... 700
Register 60: Flash Memory Protection Program Enable 8 (FMPPE8), offset 0x420 ............................... 700
Register 61: Flash Memory Protection Program Enable 9 (FMPPE9), offset 0x424 ............................... 700
Register 62: Flash Memory Protection Program Enable 10 (FMPPE10), offset 0x428 ............................ 700
Register 63: Flash Memory Protection Program Enable 11 (FMPPE11), offset 0x42C ............................ 700
Register 64: Flash Memory Protection Program Enable 12 (FMPPE12), offset 0x430 ............................ 700
Register 65: Flash Memory Protection Program Enable 13 (FMPPE13), offset 0x434 ............................ 700
Register 66: Flash Memory Protection Program Enable 14 (FMPPE14), offset 0x438 ............................ 700
Register 67: Flash Memory Protection Program Enable 15 (FMPPE15), offset 0x43C ........................... 700
Register 68: Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. 703
Register 69: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 706
Register 70: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 706
Register 71: User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 706
Register 72: User Register 3 (USER_REG3), offset 0x1EC ................................................................. 706
Micro Direct Memory Access (μDMA) ........................................................................................ 707
Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 732
Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 733
Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 734
Register 4: DMA Status (DMASTAT), offset 0x000 ............................................................................ 739
Register 5: DMA Configuration (DMACFG), offset 0x004 ................................................................... 741
Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 742
Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 743
Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ............................. 744
Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 745
Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 746
Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 747
Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 748
Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 749
Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 750
Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 751
Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 752
Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 753
Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 754
Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 755
Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 756
Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500 ................................................. 757
Register 22: DMA Channel Map Select 0 (DMACHMAP0), offset 0x510 ............................................... 758
Register 23: DMA Channel Map Select 1 (DMACHMAP1), offset 0x514 ............................................... 759
Register 24: DMA Channel Map Select 2 (DMACHMAP2), offset 0x518 ............................................... 760
Register 25: DMA Channel Map Select 3 (DMACHMAP3), offset 0x51C .............................................. 761
Register 26: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 762
Register 27: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 763
Register 28: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 764
Register 29: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 765
Register 30: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 766
37December 13, 2013
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TM4C129XNCZAD Microcontroller