Datasheet

Register 196: Cryptographic Modules Clock Gating Request (CCMCGREQ), offset 0x204 ...................... 552
Processor Support and Exception Module ............................................................................... 553
Register 1: System Exception Raw Interrupt Status (SYSEXCRIS), offset 0x000 ................................ 554
Register 2: System Exception Interrupt Mask (SYSEXCIM), offset 0x004 ........................................... 556
Register 3: System Exception Masked Interrupt Status (SYSEXCMIS), offset 0x008 ........................... 558
Register 4: System Exception Interrupt Clear (SYSEXCIC), offset 0x00C ........................................... 560
Hibernation Module ..................................................................................................................... 561
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 584
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 585
Register 3: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 586
Register 4: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 587
Register 5: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 592
Register 6: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 594
Register 7: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 596
Register 8: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 598
Register 9: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 600
Register 10: Hibernation RTC Sub Seconds (HIBRTCSS), offset 0x028 ............................................... 601
Register 11: Hibernation IO Configuration (HIBIO), offset 0x02C .......................................................... 602
Register 12: Hibernation Data (HIBDATA), offset 0x030-0x06F ............................................................ 604
Register 13: Hibernation Calendar Control (HIBCALCTL), offset 0x300 ................................................ 605
Register 14: Hibernation Calendar 0 (HIBCAL0), offset 0x310 ............................................................. 606
Register 15: Hibernation Calendar 1 (HIBCAL1), offset 0x314 ............................................................. 608
Register 16: Hibernation Calendar Load 0 (HIBCALLD0), offset 0x320 ................................................. 610
Register 17: Hibernation Calendar Load (HIBCALLD1), offset 0x324 ................................................... 612
Register 18: Hibernation Calendar Match 0 (HIBCALM0), offset 0x330 ................................................ 613
Register 19: Hibernation Calendar Match 1 (HIBCALM1), offset 0x334 ................................................ 615
Register 20: Hibernation Lock (HIBLOCK), offset 0x360 ...................................................................... 616
Register 21: HIB Tamper Control (HIBTPCTL), offset 0x400 ................................................................ 617
Register 22: HIB Tamper Status (HIBTPSTAT), offset 0x404 ................................................................ 619
Register 23: HIB Tamper I/O Control (HIBTPIO), offset 0x410 ............................................................. 621
Register 24: HIB Tamper Log 0 (HIBTPLOG0), offset 0x4E0 ................................................................ 625
Register 25: HIB Tamper Log 2 (HIBTPLOG2), offset 0x4E8 ................................................................ 625
Register 26: HIB Tamper Log 4 (HIBTPLOG4), offset 0x4F0 ................................................................ 625
Register 27: HIB Tamper Log 6 (HIBTPLOG6), offset 0x4F8 ................................................................ 625
Register 28: HIB Tamper Log 1 (HIBTPLOG1), offset 0x4E4 ................................................................ 626
Register 29: HIB Tamper Log 3 (HIBTPLOG3), offset 0x4EC ............................................................... 626
Register 30: HIB Tamper Log 5 (HIBTPLOG5), offset 0x4F4 ................................................................ 626
Register 31: HIB Tamper Log 7 (HIBTPLOG7), offset 0x4FC ............................................................... 626
Register 32: Hibernation Peripheral Properties (HIBPP) , offset 0xFC0 ................................................. 628
Register 33: Hibernation Clock Control (HIBCC), offset 0xFC8 ............................................................ 629
Internal Memory ........................................................................................................................... 630
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 654
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 655
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 656
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 659
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 662
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 664
Register 7: Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 667
35December 13, 2013
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TM4C129XNCZAD Microcontroller