Datasheet
Register 118: Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control
(SCGCUART), offset 0x718 ............................................................................................ 430
Register 119: Synchronous Serial Interface Sleep Mode Clock Gating Control (SCGCSSI), offset
0x71C ........................................................................................................................... 432
Register 120: Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C), offset 0x720 ........... 433
Register 121: Universal Serial Bus Sleep Mode Clock Gating Control (SCGCUSB), offset 0x728 ............. 435
Register 122: Ethernet PHY Sleep Mode Clock Gating Control (SCGCEPHY), offset 0x730 .................... 436
Register 123: Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN), offset 0x734 ....... 437
Register 124: Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC), offset
0x738 ........................................................................................................................... 438
Register 125: Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP), offset 0x73C .......... 439
Register 126: Pulse Width Modulator Sleep Mode Clock Gating Control (SCGCPWM), offset 0x740 ........ 440
Register 127: Quadrature Encoder Interface Sleep Mode Clock Gating Control (SCGCQEI), offset
0x744 ........................................................................................................................... 441
Register 128: EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM), offset 0x758 ..................... 442
Register 129: CRC and Cryptographic Modules Sleep Mode Clock Gating Control (SCGCCCM), offset
0x774 ........................................................................................................................... 443
Register 130: LCD Controller Sleep Mode Clock Gating Control (SCGCLCD), offset 0x790 ..................... 444
Register 131: 1-Wire Sleep Mode Clock Gating Control (SCGCOWIRE), offset 0x798 ............................ 445
Register 132: Ethernet MAC Sleep Mode Clock Gating Control (SCGCEMAC), offset 0x79C .................. 446
Register 133: Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD), offset 0x800 .......... 447
Register 134: 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER),
offset 0x804 .................................................................................................................. 448
Register 135: General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO), offset
0x808 ........................................................................................................................... 450
Register 136: Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA), offset
0x80C ........................................................................................................................... 453
Register 137: EPI Deep-Sleep Mode Clock Gating Control (DCGCEPI), offset 0x810 ............................. 454
Register 138: Hibernation Deep-Sleep Mode Clock Gating Control (DCGCHIB), offset 0x814 .................. 455
Register 139: Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control
(DCGCUART), offset 0x818 ............................................................................................ 456
Register 140: Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI), offset
0x81C ........................................................................................................................... 458
Register 141: Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C), offset
0x820 ........................................................................................................................... 459
Register 142: Universal Serial Bus Deep-Sleep Mode Clock Gating Control (DCGCUSB), offset
0x828 ........................................................................................................................... 461
Register 143: Ethernet PHY Deep-Sleep Mode Clock Gating Control (DCGCEPHY), offset 0x830 ........... 462
Register 144: Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN), offset
0x834 ........................................................................................................................... 463
Register 145: Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control (DCGCADC), offset
0x838 ........................................................................................................................... 464
Register 146: Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP), offset
0x83C ........................................................................................................................... 465
Register 147: Pulse Width Modulator Deep-Sleep Mode Clock Gating Control (DCGCPWM), offset
0x840 ........................................................................................................................... 466
Register 148: Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control (DCGCQEI), offset
0x844 ........................................................................................................................... 467
Register 149: EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM), offset 0x858 ........... 468
33December 13, 2013
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TM4C129XNCZAD Microcontroller