Datasheet

Register 38: CAN 0 Power Domain Status (CAN0PDS), offset 0x298
This register provides the status of power to the CAN0 SRAM memory array.
Note: The CAN0 memory array does not support retention and can only be turned ON and OFF.
If the memory array is currently turned on (PWRCTL = 0x3) and the power control to the
CAN0 is subsequently removed by clearing the P0 bit of the PCCAN register, the event
causes the memory array to turn off and the MEMSTAT bit in the CAN0PDS register to be
0x0 (array OFF).
CAN 0 Power Domain Status (CAN0PDS)
Base 0x400F.E000
Offset 0x298
Type RO, reset 0x0000.003F
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PWRSTATMEMSTATreservedreserved
ROROROROROROROROROROROROROROROROType
1111110000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x3ROreserved5:4
Memory Array Power Status
Displays status of the CAN0 SRAM memory
DescriptionValue
Array OFF0x0
Reserved0x1-0x2
Array On0x3
0x3ROMEMSTAT3:2
Power Domain Status
DescriptionValue
OFF0x0
Reserved0x1-0x2
ON0x3
0x3ROPWRSTAT1:0
329December 13, 2013
Texas Instruments-Advance Information
Tiva
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TM4C129XNCZAD Microcontroller