Datasheet
Register 80: Ethernet PHY Software Reset (SREPHY), offset 0x530 .................................................... 384
Register 81: Controller Area Network Software Reset (SRCAN), offset 0x534 ....................................... 385
Register 82: Analog-to-Digital Converter Software Reset (SRADC), offset 0x538 .................................. 386
Register 83: Analog Comparator Software Reset (SRACMP), offset 0x53C .......................................... 387
Register 84: Pulse Width Modulator Software Reset (SRPWM), offset 0x540 ....................................... 388
Register 85: Quadrature Encoder Interface Software Reset (SRQEI), offset 0x544 ............................... 389
Register 86: EEPROM Software Reset (SREEPROM), offset 0x558 .................................................... 390
Register 87: CRC and Cryptographic Modules Software Reset (SRCCM), offset 0x574 ......................... 391
Register 88: LCD Controller Software Reset (SRLCD), offset 0x590 .................................................... 392
Register 89: 1-Wire Software Reset (SROWIRE), offset 0x598 ............................................................ 393
Register 90: Ethernet MAC Software Reset (SREMAC), offset 0x59C .................................................. 394
Register 91: Watchdog Timer Run Mode Clock Gating Control (RCGCWD), offset 0x600 ...................... 395
Register 92: 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER), offset
0x604 ........................................................................................................................... 396
Register 93: General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO), offset
0x608 ........................................................................................................................... 398
Register 94: Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA), offset
0x60C ........................................................................................................................... 401
Register 95: EPI Run Mode Clock Gating Control (RCGCEPI), offset 0x610 ......................................... 402
Register 96: Hibernation Run Mode Clock Gating Control (RCGCHIB), offset 0x614 ............................. 403
Register 97: Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (RCGCUART),
offset 0x618 .................................................................................................................. 404
Register 98: Synchronous Serial Interface Run Mode Clock Gating Control (RCGCSSI), offset
0x61C ........................................................................................................................... 406
Register 99: Inter-Integrated Circuit Run Mode Clock Gating Control (RCGCI2C), offset 0x620 ............. 407
Register 100: Universal Serial Bus Run Mode Clock Gating Control (RCGCUSB), offset 0x628 ............... 409
Register 101: Ethernet PHY Run Mode Clock Gating Control (RCGCEPHY), offset 0x630 ...................... 410
Register 102: Controller Area Network Run Mode Clock Gating Control (RCGCCAN), offset 0x634 ......... 411
Register 103: Analog-to-Digital Converter Run Mode Clock Gating Control (RCGCADC), offset 0x638 .... 412
Register 104: Analog Comparator Run Mode Clock Gating Control (RCGCACMP), offset 0x63C ............. 413
Register 105: Pulse Width Modulator Run Mode Clock Gating Control (RCGCPWM), offset 0x640 .......... 414
Register 106: Quadrature Encoder Interface Run Mode Clock Gating Control (RCGCQEI), offset
0x644 ........................................................................................................................... 415
Register 107: EEPROM Run Mode Clock Gating Control (RCGCEEPROM), offset 0x658 ....................... 416
Register 108: CRC and Cryptographic Modules Run Mode Clock Gating Control (RCGCCCM), offset
0x674 ........................................................................................................................... 417
Register 109: LCD Controller Run Mode Clock Gating Control (RCGCLCD), offset 0x690 ....................... 418
Register 110: 1-Wire Run Mode Clock Gating Control (RCGCOWIRE), offset 0x698 ............................... 419
Register 111: Ethernet MAC Run Mode Clock Gating Control (RCGCEMAC), offset 0x69C ..................... 420
Register 112: Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD), offset 0x700 .................... 421
Register 113: 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (SCGCTIMER), offset
0x704 ........................................................................................................................... 422
Register 114: General-Purpose Input/Output Sleep Mode Clock Gating Control (SCGCGPIO), offset
0x708 ........................................................................................................................... 424
Register 115: Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA), offset
0x70C ........................................................................................................................... 427
Register 116: EPI Sleep Mode Clock Gating Control (SCGCEPI), offset 0x710 ....................................... 428
Register 117: Hibernation Sleep Mode Clock Gating Control (SCGCHIB), offset 0x714 ........................... 429
December 13, 201332
Texas Instruments-Advance Information
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