Datasheet

Register 70: MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 204
Register 71: MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 206
Register 72: MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 207
Register 73: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 207
Register 74: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 207
Register 75: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 207
Register 76: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 209
Register 77: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 209
Register 78: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 209
Register 79: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 209
Register 80: Coprocessor Access Control (CPAC), offset 0xD88 .......................................................... 212
Register 81: Floating-Point Context Control (FPCC), offset 0xF34 ........................................................ 213
Register 82: Floating-Point Context Address (FPCA), offset 0xF38 ...................................................... 215
Register 83: Floating-Point Default Status Control (FPDSC), offset 0xF3C ........................................... 216
System Control ............................................................................................................................ 230
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 266
Register 2: Device Identification 1 (DID1), offset 0x004 ..................................................................... 268
Register 3: Power-Temp Brown Out Control (PTBOCTL), offset 0x038 ............................................... 270
Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 272
Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 274
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 276
Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 278
Register 8: Power-Temperature Cause (PWRTC), offset 0x060 ......................................................... 281
Register 9: NMI Cause Register (NMIC), offset 0x064 ....................................................................... 282
Register 10: Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 284
Register 11: Run and Sleep Mode Configuration Register (RSCLKCFG), offset 0x0B0 .......................... 286
Register 12: Memory Timing Parameter Register 0 for Main Flash and EEPROM (MEMTIM0), offset
0x0C0 ........................................................................................................................... 288
Register 13: Alternate Clock Configuration (ALTCLKCFG), offset 0x138 ............................................... 291
Register 14: Deep Sleep Clock Configuration Register (DSCLKCFG), offset 0x144 ............................... 292
Register 15: Divisor and Source Clock Configuration (DIVSCLK), offset 0x148 ..................................... 295
Register 16: System Properties (SYSPROP), offset 0x14C .................................................................. 297
Register 17: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 300
Register 18: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 .................................... 302
Register 19: PLL Frequency 0 (PLLFREQ0), offset 0x160 ................................................................... 303
Register 20: PLL Frequency 1 (PLLFREQ1), offset 0x164 ................................................................... 304
Register 21: PLL Status (PLLSTAT), offset 0x168 ............................................................................... 305
Register 22: Sleep Power Configuration (SLPPWRCFG), offset 0x188 ................................................. 306
Register 23: Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C ..................................... 308
Register 24: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 310
Register 25: LDO Sleep Power Control (LDOSPCTL), offset 0x1B4 ..................................................... 311
Register 26: LDO Sleep Power Calibration (LDOSPCAL), offset 0x1B8 ................................................ 313
Register 27: LDO Deep-Sleep Power Control (LDODPCTL), offset 0x1BC ........................................... 314
Register 28: LDO Deep-Sleep Power Calibration (LDODPCAL), offset 0x1C0 ...................................... 316
Register 29: Sleep / Deep-Sleep Power Mode Status (SDPMST), offset 0x1CC .................................... 317
Register 30: Reset Behavior Control Register (RESBEHAVCTL), offset 0x1D8 ..................................... 320
Register 31: Hardware System Service Request (HSSR), offset 0x1F4 ................................................ 322
Register 32: USB Power Domain Status (USBPDS), offset 0x280 ........................................................ 323
December 13, 201330
Texas Instruments-Advance Information
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