Datasheet
Table of Contents
Revision History ............................................................................................................................. 53
About This Document .................................................................................................................... 54
Audience .............................................................................................................................................. 54
About This Manual ................................................................................................................................ 54
Related Documents ............................................................................................................................... 54
Documentation Conventions .................................................................................................................. 55
1 Architectural Overview .......................................................................................... 57
1.1 Tiva™ C Series Overview .............................................................................................. 57
1.2 TM4C129XNCZAD Microcontroller Overview .................................................................. 58
1.3 TM4C129XNCZAD Microcontroller Features ................................................................... 61
1.3.1 ARM Cortex-M4F Processor Core .................................................................................. 61
1.3.2 On-Chip Memory ........................................................................................................... 63
1.3.3 External Peripheral Interface ......................................................................................... 65
1.3.4 Cyclical Redundancy Check (CRC) ............................................................................... 67
1.3.5 Advanced Encryption Standard (AES) Accelerator .......................................................... 67
1.3.6 Data Encryption Standard (DES) Accelerator ................................................................. 68
1.3.7 Secure Hash Algorithm / Message Digest Algorithm (SHA/MD5) ..................................... 68
1.3.8 Serial Communications Peripherals ................................................................................ 69
1.3.9 System Integration ........................................................................................................ 75
1.3.10 Advanced Motion Control ............................................................................................... 83
1.3.11 Analog .......................................................................................................................... 85
1.3.12 JTAG and ARM Serial Wire Debug ................................................................................ 86
1.3.13 Packaging and Temperature .......................................................................................... 87
1.4 TM4C129XNCZAD Microcontroller Hardware Details ...................................................... 87
1.5 Kits .............................................................................................................................. 87
1.6 Support Information ....................................................................................................... 88
2 The Cortex-M4F Processor ................................................................................... 89
2.1 Block Diagram .............................................................................................................. 90
2.2 Overview ...................................................................................................................... 91
2.2.1 System-Level Interface .................................................................................................. 91
2.2.2 Integrated Configurable Debug ...................................................................................... 91
2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 92
2.2.4 Cortex-M4F System Component Details ......................................................................... 92
2.3 Programming Model ...................................................................................................... 93
2.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 93
2.3.2 Stacks .......................................................................................................................... 94
2.3.3 Register Map ................................................................................................................ 94
2.3.4 Register Descriptions .................................................................................................... 96
2.3.5 Exceptions and Interrupts ............................................................................................ 112
2.3.6 Data Types ................................................................................................................. 112
2.4 Memory Model ............................................................................................................ 112
2.4.1 Memory Regions, Types and Attributes ......................................................................... 116
2.4.2 Memory System Ordering of Memory Accesses ............................................................ 116
2.4.3 Behavior of Memory Accesses ..................................................................................... 116
2.4.4 Software Ordering of Memory Accesses ....................................................................... 117
3December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller