Datasheet

List of Registers
The Cortex-M4F Processor ........................................................................................................... 89
Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 97
Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 97
Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 97
Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 97
Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 97
Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 97
Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 97
Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 97
Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 97
Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 97
Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 97
Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 97
Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 97
Register 14: Stack Pointer (SP) ........................................................................................................... 98
Register 15: Link Register (LR) ............................................................................................................ 99
Register 16: Program Counter (PC) ................................................................................................... 100
Register 17: Program Status Register (PSR) ...................................................................................... 101
Register 18: Priority Mask Register (PRIMASK) .................................................................................. 105
Register 19: Fault Mask Register (FAULTMASK) ................................................................................ 106
Register 20: Base Priority Mask Register (BASEPRI) .......................................................................... 107
Register 21: Control Register (CONTROL) ......................................................................................... 108
Register 22: Floating-Point Status Control (FPSC) .............................................................................. 110
Cortex-M4 Peripherals ................................................................................................................. 144
Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 160
Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 162
Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 163
Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 164
Register 5: Interrupt 32-63 Set Enable (EN1), offset 0x104 ................................................................ 164
Register 6: Interrupt 64-95 Set Enable (EN2), offset 0x108 ................................................................ 164
Register 7: Interrupt 96-113 Set Enable (EN3), offset 0x10C .............................................................. 164
Register 8: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 165
Register 9: Interrupt 32-63 Clear Enable (DIS1), offset 0x184 ............................................................ 165
Register 10: Interrupt 64-95 Clear Enable (DIS2), offset 0x188 ............................................................ 165
Register 11: Interrupt 96-113 Clear Enable (DIS3), offset 0x18C .......................................................... 165
Register 12: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 166
Register 13: Interrupt 32-63 Set Pending (PEND1), offset 0x204 ......................................................... 166
Register 14: Interrupt 64-95 Set Pending (PEND2), offset 0x208 ......................................................... 166
Register 15: Interrupt 96-113 Set Pending (PEND3), offset 0x20C ....................................................... 166
Register 16: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 167
Register 17: Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284 .................................................. 167
Register 18: Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288 .................................................. 167
Register 19: Interrupt 96-113 Clear Pending (UNPEND3), offset 0x28C ............................................... 167
Register 20: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 168
Register 21: Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304 ........................................................... 168
December 13, 201328
Texas Instruments-Advance Information
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