Datasheet

Register 7: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences. If a full POK-POR is initiated, the POR bit in the RESC
register is set and all other bits are cleared. If the WDOGn, BOR or EXTRES configuration fields are
set to 0x3 in the RESBEHAVCTL register and a simulated POR is initiated, the cause of the reset
is reflected in the RESC register. A reset caused by a Hibernation wake event is also registered in
RESC and the specific wake event can be found by reading the Hibernation Raw Interrupt Status
(HIBRIS) register.
Note: The Reset Cause (RESC) register identifies if the Hibernation Module was a cause of a
reset if the HIB bit is set. If the V
DD
supply drops below the Power-On Reset threshold after
being above the threshold for 1-2 hibernate clock cycles (typical 30 to 60 µS), the RESC
register does not show the Hibernation Module as a reset cause. Software may determine
if the Hibernation module is configured and a wake-up source has triggered by reading the
Hibernation Control (HIBCTL) register and the Hibernation Raw Interrupt Status (HIBRIS)
register.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type RW, reset 0x0000.0002
16171819202122232425262728293031
MOSCFAIL
reserved
RWROROROROROROROROROROROROROROROType
-000000000000000Reset
0123456789101112131415
EXTPORBORWDT0SWWDT1HIBreservedHSSRreserved
RWRWRWRWRWRWRWRORORORORORWROROROType
010000000000-000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000ROreserved31:17
MOSC Failure Reset
Writing a 0 to this bit clears it.
DescriptionValue
When read, this bit indicates that a MOSC failure has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
0
When read, this bit indicates that the MOSC circuit was enabled
for clock validation and failed while the MOSCIM bit in the
MOSCCTL register is clear, generating a reset event.
1
-RWMOSCFAIL16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:13
December 13, 2013278
Texas Instruments-Advance Information
System Control