Datasheet

1. Once POR has completed, the PIOSC is acting as the system clock.
2. Power up the MOSC by clearing the NOXTAL bit in the MOSCCTL register.
3. If single-ended MOSC mode is required, the MOSC is ready to use. If crystal mode is required,
clear the PWRDN bit and wait for the MOSCPUPRIS bit to be set in the Raw Interrupt Status
(RIS), indicating MOSC crystal mode is ready.
4. Set the OSCSRC field to 0x3 in the RSCLKCFG register at offset 0x0B0.
5. If the application also requires the MOSC to be the deep-sleep clock source, then program the
DSOSCSRC field in the DSCLKCFG register to 0x3.
6. Write the PLLFREQ0 and PLLFREQ1 registers with the values of Q, N, MINT, and MFRAC to
the configure the desired VCO frequency setting.
7. Write the MEMTIM0 register to correspond to the new system clock setting.
8. Wait for the PLLSTAT register to indicate the PLL has reached lock at the new operating point
(or that a timeout period has passed and lock has failed, in which case an error condition exists
and this sequence is abandoned and error processing is initiated).
9. Write the RSCLKCFG register's PSYSDIV value, set the USEPLL bit to enabled, and MEMTIMU
bit.
If it is necessary to keep the MOSC powered on during automatic (deep-sleep) or accidental power
down, then the MOSCDPD bit should be set to 0x1. Otherwise, if the MOSCDPD bit is set to 0x0, the
MOSC is powered off when deep-sleep is entered or automatic power down occurs. The following
table describes the relationship between the PWRDN bit in the MOSCCTL register and the MOSCDPD
bit in the DSCLKCFG register:
Table 5-10. MOSC Configurations
ResultMOSCDPD fieldPWRDN bit
MOSC is powered ON in run and sleep modes, but is disabled in accidental power down,
when the PWRDN bit is set in the MOSCCTL register, or in deep-sleep mode only if it is not
the deep-sleep clock source (DSOSCSRC !==0x3).
00
MOSC is powered and running in run, sleep and deep-sleep modes.10
MOSC is powered off, and does not run in any mode. Please note, that in this configuration,
when the MOSC is disabled, the MOSC must not be chosen as a clock source or indeterminate
results occur.
01
MOSC runs and does not disable itself in run, sleep, and deep-sleep modes regardless of
the fact that the PWRDN bit is set.
11
Note: The MOSCDPD bit has an effect in all modes of operation
To change the system clock frequency by changing its corresponding PSYSDIV or OSYSDIV value,
a user must ensure timing parameters to memory are within range through the following steps:
1. If the change in system clock frequency changes the operational range of the timing parameters,
the MEMTIM0 register must be updated. If so, write the timing configuration register, MEMTIM0,
setting the value to correspond to the final SYSCLK frequency (f
VCO
/new SYSDIV or f
OSC
).
Otherwise the MEMTIM0 register should not be changed.
257December 13, 2013
Texas Instruments-Advance Information
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TM4C129XNCZAD Microcontroller