Datasheet

Peripheral Memory Power Control
When Deep-Sleep is entered, users have the capability to reduce power further in peripheral modules
which have their own associated memory array. Many of these peripherals can be programmed to
enable a low-power retention mode or a power down of their associated peripheral SRAM array. If
retention is supported and the PWRCTL bit field of the module's xMPC register is programmed to
0x1, the associated peripheral SRAM memory array is put in retention mode in which no accesses
can be performed. When the PWRCTL bit is set to 0x0 in Deep-Sleep mode, the memory is powered
off, the contents are lost and the SRAM is not accessible. The peripheral's Power Domain Status
(xPDS) can be read to determine the status of the peripheral's memory array as well as the
peripheral's current power domain status. The table below lists the capabilities of peripherals with
SRAM arrays during low power modes.
Table 5-8. Peripheral Memory Power Control
Memory Array Power Down Capability?Memory Retention Capability?Module
YesYesUSB
Yes
(only when power domain is off, PCEMAC register = 0x0)
NoEMAC
NoNoLCD
YesNoCAN
LDO Power Control
Note: While the device is connected through JTAG, the LDO control settings for Sleep or
Deep-Sleep are not available and will not be applied.
Software can configure the LDOSPCTL register (see page 311) and/or the LDODPCTL register (see
page 314) to dynamically raise or lower the LDO voltage in Sleep and Deep-Sleep mode depending
on whether an increase in performance or reduction in power consumption is required. The VLDO
field in the LDOSPCTL register is set to 1.2 V as default. The LDODPCTL register is set to an LDO
voltage of 0.9 V as default. If an application requires performance over power consumption in
Deep-Sleep, the Deep-Sleep LDO voltage can be configured to a higher voltage than 0.9 V during
System Control initialization by setting the VADJEN bit and programming the VLDO field of the
LDODPCTL register.
Before the LDO level is lowered in Sleep or Deep-Sleep, the system clock must be configured to
an acceptable frequency in the RSCLKCFG register for Sleep mode and in DSLPCLKCFG for
Deep-Sleep mode. The following table shows the maximum System Clock and PIOSC frequency
with respect to the LDO voltage.
Table 5-9. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage
PIOSCMaximum System Clock FrequencyOperating Voltage (LDO)
16 MHz120 MHz1.2
16 MHz30 MHz0.9
The LDO Power Calibration registers, LDOSPCAL and LDODPCAL, provide suggested values for
the LDO in the various modes. If software requests an LDO value that is too low or too high, the
value is not accepted and an error is reported in the SDPMST register.
Note: When using the USB module, the LDO must be configured to 1.2 V.
December 13, 2013254
Texas Instruments-Advance Information
System Control