Datasheet

Table 5-7 on page 249 provides examples of the programming expected for the PLLFREQ0 and
PLLFREQ1 registers. The first column specifies the input crystal frequency and the last column
displays the PLL frequency given the values of MINT and N, when Q=0.
Table 5-7. Actual PLL Frequency
a
PLL Frequency
(MHz)
Reference
Frequency
(MHz)
b
NMINT (Hexadecimal
Value)
MINT (Decimal
Value)
Crystal
Frequency
(MHz)
32050x00x40645
32020x20x351606
32080x00x28408
320100x00x203210
32040x20x508012
320160x00x142016
32020x80xA016018
320200x00x101620
32080x20x284024
32050x40x406425
48050x00x60965
48060x00x50806
48080x00x3C608
480100x00x304810
480120x00x284012
480160x00x1E3016
48060x20x508018
480200x00x182420
480240x00x142024
48050x40x609625
a. For all examples listed, Q=0
b. For a given crystal frequency, N should be chosen such that the reference frequency is within 4 to 30 MHz.
PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is T
READY
(see Table
32-16 on page 2115). During the relock time, the affected PLL is not usable as a clock reference.
Software can poll the LOCK bit in the PLL Status (PLLSTAT) register to determine when the PLL
has locked.
Modification of the PLL VCO frequency may not be performed while the PLL serves as a clock
source to the system. All changes to the PLL must be performed using a different clock source until
the PLL has locked frequency. Thus, changing the PLL VCO frequency must be done as a sequence
from PLL to PIOSC/MOSC and then PIOSC/MOSC to new PLL.
Hardware is provided to keep the PLL from being used as a system clock until the T
READY
condition
is met after one of the two changes above. It is the user's responsibility to have a stable clock source
(like the main oscillator) before the RSCLKCFG register is re-programmed to enable the PLL.
Software can use many methods to ensure that the system is clocked from the PLL, including
periodically polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register at offset 0x050, and
enabling the PLL Lock interrupt in the Interrupt Mask Control (IMC) register at offset 0x054.
249December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller