Datasheet

The PIOSC generates a 16-MHz clock with a ±3% accuracy. At the factory, the PIOSC is set to 16
MHz at room temperature, however, the frequency can be trimmed for other voltage or temperature
conditions using software in the following ways:
■ Default calibration: clear the UTEN bit and set the UPDATE bit in the Precision Internal Oscillator
Calibration (PIOSCCAL) register.
■ User-defined calibration: The user can program the UT value to adjust the PIOSC frequency. As
the UT value increases, the generated period increases. To commit a new UT value, first set the
UTEN bit, then program the UT field, and then set the UPDATE bit. The adjustment finishes within
a few clock periods and is glitch free.
■ Automatic calibration using the enable 32.768-kHz oscillator from the Hibernation module: Set
the CAL bit in the PIOSCCAL register; the results of the calibration are shown in the RESULT
field in the Precision Internal Oscillator Statistic (PIOSCSTAT) register. After calibration is
complete, the PIOSC is trimmed using the trimmed value returned in the CT field.
5.2.5.4 Main Oscillator (MOSC)
The main oscillator supports the use of crystals from 5 to 25 MHz. The system control's RSCLKCFG
register can be configured to specify the MOSC as the system clock or as the PLL input source.
The MOSC can be selected as the oscillator source by programming the OSCRC bit in the RSCLKCFG
register. The NOXTAL bit in the MOSCCTL register allows the user to turn off power to the MOSC
if no crystal is connected reducing power draw from the MOSC circuit.
Main Oscillator Verification Circuit
The clock control includes circuitry to ensure that the main oscillator is running at the appropriate
frequency. The circuit monitors the main oscillator frequency and signals if the frequency is outside
of the allowable band of attached crystals.
The detection circuit is enabled using the CVAL bit in the Main Oscillator Control (MOSCCTL)
register. If this circuit is enabled and detects an error, and if the MOSCIM bit in the MOSCCTL register
is clear, then the following sequence is performed by the hardware:
1. The MOSCFAIL bit in the Reset Cause (RESC) register is set.
2. The system clock is switched from the main oscillator to the PIOSC.
3. An internal system reset is initiated.
4. Reset is deasserted and the processor is directed to the NMI handler during the reset sequence.
5.2.5.5 PLL
The PLL has two modes of operation: Normal and Power-Down
■ Normal: The PLL oscillates based on the values in the PLLFREQ0 and PLLFREQ1 registers
and drives the output.
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the PLLPWR bit in the PLLFREQ0 register (see page 303).
247December 13, 2013
Texas Instruments-Advance Information
Tiva
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TM4C129XNCZAD Microcontroller