Datasheet

■ A gated system clock acts as the clock source to the Control and Status registers (CSR) of the
Ethernet MAC. The SysClk frequency for Run, Sleep and Deep Sleep mode is programmed in
the System Control module.
■ The PHY receives the main oscillator (MOSC) which must be 25 MHz ± 50 ppm for proper
operation. The MOSC source can be a single-ended source or a crystal.
MII Interface Clocking
Four clock inputs are driven into the Ethernet MAC when the MII configuration is enabled. The clocks
are described as follows (see “MII Interface” on page 1589 for more information):
■ Gated system clock (SysClk): The SysClk signal acts as the clock source to the Control and
Status registers (CSR) of the Ethernet MAC. The SysClk frequency for Run, Sleep and Deep
Sleep mode is programmed in the System Control module.
■ MOSC: A gated version of the MOSC clock is provided as the Precision Time Protocol (PTP)
reference clock (PTPREF_CLK). The MOSC clock source can be a single-ended source on the
OSC0 pin or a crystal on the OSC0 and OSC1 pins. When advanced timestamping is used and
the Precision Timer Protocol (PTP) module has been enabled by setting the PTPCEN bit in the
EMACCC register, the MOSC drives PTPREF_CLK. PTPREF_CLK has a minimum frequency
requirement of 5 MHz and a maximum frequency of 25 MHz. Refer to “IEEE 1588 and Advanced
Timestamp Function” on page 1631 for more information.
■ EN0RXCK: This clock signal is driven by the external PHY oscillator and is either 2.5 or 25 MHz
depending on whether the device is operating at 10 Mbps or 100 Mbps.
■ EN0TXCK This clock signal is driven by the external PHY oscillator and is either 2.5 or 25 MHz
depending on whether the device is operating at 10 Mbps or 100 Mbps.
RMII Interface Clocking
There are three clock sources that interface to the Ethernet MAC in an RMII configuration (see “RMII
Interface” on page 1590 for more information):
■ Gated system clock (SysClk): The SysClk signal acts as the clock source to the Control and
Status registers (CSR) of the Ethernet MAC. The SysClk frequency for Run, Sleep and Deep
Sleep mode is programmed in the System Control module.
■ MOSC: A gated version of the MOSC clock is provided as the Precision Time Protocol (PTP)
reference clock (PTPREF_CLK). The MOSC clock source can be a single-ended source on the
OSC0 pin or a crystal on the OSC0 and OSC1 pins. When advanced timestamping is used and
the PTP module has been enabled by setting the PTPCEN bit in the EMACCC register, the MOSC
drives PTPREF_CLK. PTPREF_CLK has a minimum frequency requirement of 5 MHz and a
maximum frequency of 25 MHz. Refer to “IEEE 1588 and Advanced Timestamp
Function” on page 1631 for more information.
■ EN0REF_CLK: When using RMII, a 50 MHz external reference clock must drive the EN0REF_CLK
input signal and the external PHY. Depending on the configuration of the FES bit in the Ethernet
MAC Configuration (EMACCFG) register, the reference clock input (EN0REF_CLK) is divided
by 20 for 10 Mbps or 2 for 100 Mbps operation and used as the clock for receive and transmit
data.
245December 13, 2013
Texas Instruments-Advance Information
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TM4C129XNCZAD Microcontroller