Datasheet

Peripheral Clock Sources
In addition to the main clock tree described above, the ADC, USB, Ethernet, PWM, UART, and
QSSI all have a Clock Control register in their register map at offset 0xFC8 that can be used to
control the clock generation for the module.
ADC Clock Control
The ADC digital block is clocked by the system clock and the ADC analog block is clocked from a
separate conversion clock (ADC clock). The ADC clock frequency is 16 MHz and can generate a
conversion rate of 1 Msps. There are three sources for the ADC clock:
■ The PLL VCO (f
VCO
) can be used if the CS bit field is 0x0 in the ADC Clock Configuration
(ADCCC) register and the CLKDIV bit field is configured in the same register.
■ The PIOSC can be used directly to provide a conversion rate near 1 Ms/s. To use the PIOSC,
the CS field in the ADCCC register needs to be set to 0x1 and the ALTCLK field should be
programmed to 0x0 in the Alternate Clock Configuration (ALTCLKCFG) register.
■ The Main Oscillator (MOSC) - The attached crystal must be 16 MHz for a 1 Msps conversion
rate.
Note: If the ADC module is not using the PIOSC as the clock source, the system clock must be
at least 16 MHz.
USB Clock Control
When the USB module uses the integrated USB PHY, the MOSC must be the clock source, either
with or without using the PLL, and the system clock must be at least 30 MHz. In addition, only integer
divisors should be used to achieve the 60 MHz USB clock source. Fractional divisors may increase
jitter and compromise USB function. The USB Clock Control Register (USBCC) register contains
a CLKDIV bit field which can be programmed to specify the divisor used to reduce the PLL VCO
output to the 60 MHz clock source required for the serialization/deserialization module of the USB
controller.
In ULPI mode, if the clock source to the USB is internal, then the USB0CLK pin is an output to the
external ULPI PHY. If the USB clock source is external then, the USB0CLK pin functions as an input
from the external ULPI PHY.
Ethernet Clock Control
Available clock sources are dependent on the interface chosen. The following sections describe the
clock control for the various interfaces.
The Ethernet Controller Module and Integrated PHY receive two clock inputs. A gated system clock
acts as the clock source to the Control and Status registers (CSR) of the Ethernet MAC and must
be 20 MHz or greater for correct operation. The SYSCLK frequency for Run, Sleep and Deep Sleep
mode is programmed in the System Control module. See “Ethernet Clock Control” on page 1588 for
more information.
PHY Interface Clocking
The Ethernet Controller Module and Integrated PHY receive two clock inputs (see “PHY
Interface” on page 1588 for more information):
December 13, 2013244
Texas Instruments-Advance Information
System Control