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ManualsBrandsTEXAS INSTRUMENTS ManualsDev KitsPCB design board

Table 23-5. CAN Register Map ........................................................................................... 1553

Table 24-1. Ethernet Signals (212BGA) .............................................................................. 1587

Table 24-2. MII and RMII Interface Signals .......................................................................... 1591

Table 24-3. Transmit Descriptor 0 (TDES0) ......................................................................... 1605

Table 24-4. Transmit Descriptor 1 (TDES1) ......................................................................... 1607

Table 24-5. Transmit Descriptor 2 (TDES2) ......................................................................... 1608

Table 24-6. Transmit Descriptor 3 (TDES3) ......................................................................... 1609

Table 24-7. Receive Descriptor 0 (RDES0) ......................................................................... 1609

Table 24-8. RDES0 Checksum Offload bits ......................................................................... 1611

Table 24-9. Receive Descriptor 1 (RDES1) ......................................................................... 1611

Table 24-10. Receive Descriptor 2 (RDES2) ......................................................................... 1612

Table 24-11. Receive Descriptor 3 (RDES3) ......................................................................... 1612

Table 24-12. Transmit Descriptor 2 (TDES2) with 1588-2005 Timestamping Enabled .............. 1612

Table 24-13. Transmit Descriptor 3 (TDES3) with 1588-2005 Timestamping Enabled .............. 1613

Table 24-14. Receive Descriptor 2 (RDES2) with 1588-2005 Timestamping Enabled ............... 1613

Table 24-15. Receive Descriptor 3 (RDES3) with 1588-2005 Timestamping Enabled ............... 1613

Table 24-16. Enhanced Transmit Descriptor 0 (TDES0) ......................................................... 1614

Table 24-17. Enhanced Transmit Descriptor 1 (TDES1) ......................................................... 1617

Table 24-18. Enhanced Transmit Descriptor 2 (TDES2) ......................................................... 1617

Table 24-19. Enhanced Transmit Descriptor 3 (TDES3) ......................................................... 1618

Table 24-20. Enhanced Transmit Descriptor 6 (TDES6) ......................................................... 1618

Table 24-21. Enhanced Transmit Descriptor 7 (TDES7) ......................................................... 1618

Table 24-22. Enhanced Receive Descriptor 0 (RDES0) .......................................................... 1619

Table 24-23. Enhanced Receive Descriptor 1 (RDES1) .......................................................... 1621

Table 24-24. Enhanced Receive Descriptor 2 (RDES2) .......................................................... 1622

Table 24-25. Enhanced Receive Descriptor 3 (RDES3) .......................................................... 1622

Table 24-26. Enhanced Received Descriptor 4 (RDES4) ........................................................ 1622

Table 24-27. Enhanced Receive Descriptor 6 (RDES6) .......................................................... 1624

Table 24-28. Enhanced Receive Descriptor 7 (RDES7) .......................................................... 1624

Table 24-29. TX MAC Flow Control ...................................................................................... 1628

Table 24-30. RX MAC Flow Control ...................................................................................... 1628

Table 24-31. VLAN Match Status .......................................................................................... 1640

Table 24-32. CRC Replacement Based on Bit 27 and Bit 24 of TDES0 ................................... 1642

Table 24-33. Forced Mode Configurations ............................................................................. 1650

Table 24-34. Advertised Mode Configurations ....................................................................... 1650

Table 24-35. EMACPC to PHY Register Mapping .................................................................. 1656

Table 24-36. Ethernet Register Map ..................................................................................... 1658

Table 25-1. USB Signals (212BGA) .................................................................................... 1840

Table 25-2. List of Registers ............................................................................................... 1841

Table 26-1. LCD Signals (212BGA) .................................................................................... 1848

Table 26-2. LCD External Signal Details .............................................................................. 1849

Table 26-3. LCD Alternate Signal Functions in LIDD Mode ................................................... 1850

Table 26-4. LIDD I/O Name Map ........................................................................................ 1853

Table 26-5. Operation Modes Supported by Raster Controller .............................................. 1854

Table 26-6. Type Encoding in Palette Entry 0 Buffer ............................................................. 1859

Table 26-7. Intensities and Modulation Rates ...................................................................... 1863

Table 26-8. Number of Colors/Shades of Gray Available on Screen ...................................... 1864

Table 26-9. LCD Register Map ........................................................................................... 1868

December 13, 201324

Texas Instruments-Advance Information

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