Datasheet

The watchdog timer can be configured to generate an interrupt or a non-maskable interrupt to the
microcontroller on its first time-out and to generate a system reset or power-on reset on its second
time-out.
After the watchdog's first time-out event, the 32-bit watchdog counter is reloaded with the value of
the Watchdog Timer Load (WDTLOAD) register and resumes counting down from that value. If
the timer counts down to zero again before the first time-out interrupt is cleared, and watchdog reset
generation has been enabled through the RESEN bit in the Watchdog Control Register (WDTCTL),
the watchdog timer asserts its reset signal to the microcontroller. The reset generated can be a full
Power-On Reset or a system reset depending on the value programmed in WDOGn bit field of the
Reset Behavior Control Register (RESBEHAVCTL). If the RESEN bit of the WDTCTL register is
set to 1 and the WDOGn bit field of the RESBEHAVCTL register is programmed to 0x3 a full POR is
initiated; if WDOGn set to 0x2, then a system reset is issued. When WDOGn is set to a 0x0 or 0x1,
then the watchdog time performs its default operation upon assertion, which is issuing a full POR.
The watchdog timer Power-On Reset sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal POR reset is asserted.
3. The internal reset is released and the core executes a full initialization of the device. Upon
completion, the core loads from memory the initial stack pointer, the initial program counter,
and the first instruction designated by the program counter, and then begins execution. Refer
to “Reset” on page 2112 for watchdog timeout internal reset deassertion timing.
The watch dog timer system reset sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the microcontroller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
For more information on the Watchdog Timer module, see “Watchdog Timers” on page 1175.
The watchdog reset timing is shown in Figure 32-13 on page 2114.
5.2.2.8 Hibernation Module Reset
When the Hibernation module has been configured and powered by an initial "cold" POR and is
subsequently put into hibernation mode, a wake event (not including an external reset pin wake)
causes the module to generate a system reset. This reset signal resets all circuitry on the device
with the exception of the Hibernation module. All Hibernation module registers retain their values
after this reset.
When the Hibernation module receives a wake event and V
DD
is enabled, a system reset sequence
occurs as follows:
1. The HIB bit in the RESC register is set.
2. An internal reset is asserted.
237December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller