Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsDev KitsPCB design board

Table 15-8. Continuing a Prior HMAC ................................................................................. 1078

Table 15-9. SHA-1 Apply on the Key ................................................................................... 1079

Table 15-10. Interrupt Mode ................................................................................................. 1079

Table 15-11. DMA Mode ...................................................................................................... 1080

Table 15-12. SHA/MD5 Register Map ................................................................................... 1081

Table 15-13. SHA/MD5 Inner/Outer Digest/HMAC Key Register Mapping ............................... 1083

Table 16-1. Available CCP Pins .......................................................................................... 1103

Table 16-2. General-Purpose Timers Signals (212BGA) ....................................................... 1104

Table 16-3. General-Purpose Timer Capabilities .................................................................. 1106

Table 16-4. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes ........ 1107

Table 16-5. 16-Bit Timer With Prescaler Configurations ........................................................ 1109

Table 16-6. Counter Values When the Timer is Enabled in RTC Mode .................................. 1109

Table 16-7. Counter Values When the Timer is Enabled in Input Edge-Count Mode ............... 1110

Table 16-8. Counter Values When the Timer is Enabled in Input Event-Count Mode .............. 1112

Table 16-9. Counter Values When the Timer is Enabled in PWM Mode ................................. 1113

Table 16-10. Timeout Actions for GPTM Modes ..................................................................... 1117

Table 16-11. Timers Register Map ........................................................................................ 1122

Table 17-1. Watchdog Timers Register Map ........................................................................ 1178

Table 18-1. ADC Signals (212BGA) .................................................................................... 1202

Table 18-2. Samples and FIFO Depth of Sequencers .......................................................... 1204

Table 18-3. Sample and Hold Width in ADC Clocks ............................................................. 1206

Table 18-4. R

and F

CONV

Values with Varying N

Values and T

ADC

= 1/16 MHz .................. 1207

Table 18-5. Differential Sampling Pairs ............................................................................... 1213

Table 18-6. ADC Register Map ........................................................................................... 1221

Table 18-7. Sample and Hold Width in ADC Clocks ............................................................. 1275

Table 18-8. Sample and Hold Width in ADC Clocks ............................................................. 1287

Table 18-9. Sample and Hold Width in ADC Clocks ............................................................. 1295

Table 19-1. UART Signals (212BGA) .................................................................................. 1311

Table 19-2. Flow Control Mode ........................................................................................... 1317

Table 19-3. UART Register Map ......................................................................................... 1322

Table 20-1. SSI Signals (212BGA) ...................................................................................... 1377

Table 20-2. QSSI Transaction Encodings ............................................................................ 1380

Table 20-3. SSInFss Functionality ...................................................................................... 1381

Table 20-4. Legacy Mode TI, Freescale SPI Frame Format Features .................................... 1383

Table 20-5. SSI Register Map ............................................................................................. 1391

Table 21-1. I2C Signals (212BGA) ...................................................................................... 1426

Table 21-2. Examples of I

C Master Timer Period Versus Speed Mode ................................. 1433

Table 21-3. Examples of I

C Master Timer Period in High-Speed Mode ................................ 1434

Table 21-4. Inter-Integrated Circuit (I

C) Interface Register Map ........................................... 1449

Table 21-5. Write Field Decoding for I2CMCS[6:0] ............................................................... 1457

Table 22-1. 1-Wire Signals (212BGA) ................................................................................. 1506

Table 22-2. Active Time Periods in Overdrive Mode ............................................................. 1510

Table 22-3. Bit Field Definitions for 1-Wire Timing and Override (ONEWIRETIM) Register ..... 1510

Table 22-4. OWIRE Register Map ....................................................................................... 1515

Table 23-1. Controller Area Network Signals (212BGA) ........................................................ 1536

Table 23-2. Message Object Configurations ........................................................................ 1541

Table 23-3. CAN Protocol Ranges ...................................................................................... 1549

Table 23-4. CANBIT Register Values .................................................................................. 1549

23December 13, 2013

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TM4C129XNCZAD Microcontroller