Datasheet
Table 10-6. GPIO Pins With Non-Zero Reset Values .............................................................. 787
Table 10-7. GPIO Register Map ........................................................................................... 787
Table 10-8. GPIO Pins With Non-Zero Reset Values .............................................................. 801
Table 10-9. GPIO Pins With Non-Zero Reset Values .............................................................. 807
Table 10-10. GPIO Pins With Non-Zero Reset Values .............................................................. 809
Table 10-11. GPIO Pins With Non-Zero Reset Values .............................................................. 812
Table 10-12. GPIO Pins With Non-Zero Reset Values .............................................................. 818
Table 10-13. GPIO Drive Strength Options .............................................................................. 831
Table 11-1. External Peripheral Interface Signals (212BGA) ................................................... 848
Table 11-2. EPI Interface Options ......................................................................................... 853
Table 11-3. EPI SDRAM x16 Signal Connections .................................................................. 854
Table 11-4. CSCFGEXT + CSCFG Encodings ...................................................................... 858
Table 11-5. Dual- and Quad- Chip Select Address Mappings ................................................. 859
Table 11-6. Chip Select Configuration Register Assignment ................................................... 860
Table 11-7. Capabilities of Host Bus 8 and Host Bus 16 Modes .............................................. 860
Table 11-8. EPI Host-Bus 8 Signal Connections .................................................................... 862
Table 11-9. EPI Host-Bus 16 Signal Connections .................................................................. 864
Table 11-10. PSRAM Fixed Latency Wait State Configuration .................................................. 870
Table 11-11. Data Phase Wait State Programming .................................................................. 874
Table 11-12. EPI General-Purpose Signal Connections ........................................................... 880
Table 11-13. External Peripheral Interface (EPI) Register Map ................................................. 885
Table 11-14. CSCFGEXT + CSCFG Encodings ...................................................................... 911
Table 11-15. CSCFGEXT + CSCFG Encodings ...................................................................... 917
Table 12-1. Endian Configuration ......................................................................................... 978
Table 12-2. Endian Configuration with Bit Reversal ................................................................ 978
Table 12-3. CCM Register Map ............................................................................................ 980
Table 13-1. Key-Block-Round Combinations ......................................................................... 990
Table 13-2. Interrupts and Events ......................................................................................... 999
Table 13-3. AES Module Performance (Input/Output Block Size = 128) ................................. 1000
Table 13-4. AES Module Packet Mode Switch Overhead ..................................................... 1001
Table 13-5. AES Register Map ........................................................................................... 1007
Table 13-6. AES Key Register Descriptions ......................................................................... 1010
Table 14-1. Key Repartition ................................................................................................ 1039
Table 14-2. DES Reset Description ..................................................................................... 1041
Table 14-3. DES Global Initialization ................................................................................... 1043
Table 14-4. DES Algorithm Type Configuration .................................................................... 1044
Table 14-5. 3DES Algorithm Type Configuration .................................................................. 1044
Table 14-6. DES Interrupt Mode ......................................................................................... 1045
Table 14-7. DES DMA Mode .............................................................................................. 1045
Table 14-8. DES Register Map ........................................................................................... 1047
Table 14-9. DES Key Register Mapping .............................................................................. 1049
Table 15-1. Interrupts and Events ....................................................................................... 1070
Table 15-2. SHA/MD5 Module Algorithm Selection .............................................................. 1070
Table 15-3. Outer Digest Registers ..................................................................................... 1071
Table 15-4. Inner Digest Registers ...................................................................................... 1072
Table 15-5. SHA Digest Processed in Three Passes ............................................................ 1074
Table 15-6. SHA Digest Processed in One Pass .................................................................. 1074
Table 15-7. SHA/MD5 Performance .................................................................................... 1076
December 13, 201322
Texas Instruments-Advance Information
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