Datasheet

Figure 32-64. LCD Raster-Mode Control Signal Deactivation
LCDLP (HSYNC)
LCDCP
(active mode)
LCDDATA[23:0]
(active mode)
PPLMSB + PPLLSB
16 x (1 to 2048)
HBP
(1 to 256)
Line 1
(1 to 256)
HFP
(1 to 64)
HSW
Line 1 for active
Line 2 for passive
LCDFP (VSYNC)
LCDCP
(passive mode)
LCDAC
LCDDATA[7:0]
(passive mode)
1, 1 2, 2
P, 2
P, 1
2, 1 1, 2
L30
L30
L28
L26
L24
L25
L21
L22
L23
VBP = 0
VFP = 0
VWS = 1
PPLMSB + PPLLSB
16 x (1 to 2048)
L31
L21
L22
L23
2, 1
P, 1
1, 1
L24
L25
32.22 Analog Comparator
Table 32-70. Analog Comparator Characteristics
ab
UnitMaxNomMinParameter NameParameter
VV
DDA
-GNDAInput voltage rangeV
INP
,V
INN
c
VV
DDA
-GNDAInput common mode voltage rangeV
CM
mV±50
d
±10-Input offset voltageV
OS
µA2.0--Input leakage current over full voltage rangeI
INP
,I
INN
dB-50-Common mode rejection ratioC
MRR
µs1.0
e
--Response timeT
RT
µs10--Comparator mode change to Output ValidT
MC
a. Best design practices suggest that static or quiet digital I/O signals be configured adjacent to sensitive analog inputs to
reduce capacitive coupling and cross talk.
b. To achieve best analog results, the source resistance driving the analog inputs, V
INP
and V
INN
, should be kept low.
c. The external voltage inputs to the Analog Comparator are designed to be highly sensitive and can be affected by external
noise on the board. For this reason, V
INP
and V
INN
must be set to different voltage levels during idle states to ensure the
analog comparator triggers are not enabled. If an internal voltage reference is used, it should be set to a mid-supply
2171December 13, 2013
Texas Instruments-Advance Information
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TM4C129XNCZAD Microcontroller