Datasheet

Table 32-69. Switching Characteristics Over Recommended Operating Characteristics for
LCD Raster Mode (continued)
UnitMaxNomMinParameter NameParameterParameter No.
ns7.3-2.0Delay time from LCDCP to
LCDDATA[23:0] invalid (write)
T
DLYINV
L25
ns7.0-1.9Delay time, LCDCP to LCDACT
DLYHAC
L26
ns3.3-0.5LCDAC transition timeT
TRANAC
L27
ns6.5-1.7Delay time from LCDCP high to LCDFPT
DLYFP
L28
ns3.3-0.5LCDFP transition timeT
TRANFP
L29
ns6.8-2.0Delay time from LCDCP high to LCDLPT
DLYLP
L30
ns3.3-0.5LCDLP transition timeT
TRANLP
L31
ns3.3-0.5LCDCP transition timeT
TRANCP
L32
ns3.3-0.5LCDDATA transition timeT
TRANDATA
L33
Frame-to-frame timing is derived through the following parameters in the LCD Raster Timing 1
(LCDRASTRTIM1) register:
■ Vertical front porch (VFP)
■ Vertical sync pulse width (VSW)
■ Vertical back porch (VBP)
■ Lines per panel (MSBLPP + LPP)
Line-to-line timing is derived through the following parameters in the LCD Raster Timing 0
(LCDRASTRTIM0) register:
■ Horizontal front porch (HFP)
■ Horizontal sync pulse width (HSW)
■ Horizontal back porch (HBP)
■ Pixels per panel (PPLMSB + PPLLSB)
LCDAC timing is derived through the following parameter in the LCD Raster Timing 2
(LCDRASTRTIM2) register:
■ AC bias frequency (ACBF)
The display format produced in raster mode is shown in Figure 32-60 on page 2167. An entire frame
is delivered one line at a time. The first line delivered starts at data pixel (1, 1) and ends at data
pixel (P, 1). The last line delivered starts at data pixel (1, L) and ends at data pixel (P, L). The
beginning of each new frame is denoted by the activation of IO signal LCDFP (VSYNC). The beginning
of each new line is denoted by the activation of IO signal LCDLP (HSYNC).
December 13, 20132166
Texas Instruments-Advance Information
Electrical Characteristics