Datasheet

Figure 32-56. Motorola 6800 Graphic Display Mode Status (Synchronous & Asynchronous
Operation)
LCD_D [15:0]ATA
LCDAC
(CS0)
LCDFP
(ALE)
LCDLP
(DIR)
LCDCP
(RS/WS)
Read
Status
LCDMCLK
(CS1) Async Mode
L6
L6
L12 L12
L6
L14
L15
L6
RDSU
(0−31)
RDDUR
(1−63)
GAP
(0−3)
RDHOLD
(1−15)
L16
L18
L17
L8 L8
L13
L9
L7
L1
L3
L2
L7
L19
LCDMCLK
Sync Mode
(internal MCLK)
32.21.1.3 Intel 8080 Mode
Intel mode can be configured to perform asynchronous operations or synchronous operations. When
configured in asynchronous mode, LCDMCLK is not required, so it performs the CS1 function. When
configured in synchronous mode, MCLK is available externally through the signal LCDMCLK. Note
that in asynchronous mode the internal MCLK shown represents the internal clock that sequences
the other signals. All of the parameter values associated with the following figures can be found in
Table 32-67 on page 2156 and Table 32-68 on page 2157.
Note: The acronyms WRSU, WRDUR, WRHOLD and GAP in the following figures correspond to the
bitfields of the LIDDCS0CFG register described in “LCD Interface Display Driver (LIDD
Mode)” on page 2156.
December 13, 20132162
Texas Instruments-Advance Information
Electrical Characteristics