Datasheet

Table 32-67. LCD Switching Characteristics (continued)
UnitMaxNomMinParameter NameParameterParameter
No.
ns8.4--Delay time of internal MCLK to LCDCPT
DLYCP
L12
ns5.9--LCDCP transition timeT
TRANCP
L13
ns11.7--Delay time from internal MCLK high to
LCDDATA[15:0] high-Z (read cycle)
T
DLYDZ
L14
ns11.0--Delay time from internal MCLK high to
LCDDATA[15:0] active (read cycle)
T
DLYDD
L15
ns5.9--Internal MCLK transition timeT
TRANMCLK
L19
ns5.9--LCDDATA transition time from one data packet
to next.
T
TRANPKT
L20
Table 32-68. Timing Requirements for LCDDATA in LIDD Mode
UnitMaxNomMinParameter NameParameterParameter No.
ns--20LCDDATA[15:0] setup time (read) before
internal MCLK high
T
STDATA
L16
ns--0LCDDATA[15:0] hold time (read) after
internal MCLK high
T
HTDATA
L17
ns--5.9LCDDATA read transition timeT
TRANRDATA
L18
32.21.1.1 Hitachi Mode
Hitachi mode is an asynchronous mode which does not use an external LCDMCLK and allows for
full programmability of the read and write strobes, data and enables through the LIDDCS0CFG
register. Note that in addition to the parameter delays configured in the LIDDCS0CFG register, the
delay times in the associated figures shown below that are from the internal MCLK to the signal
output must be added to the programmed delays for full timing information. All of the parameter
values associated with the following figures can be found in Table 32-67 on page 2156 and Table
32-68 on page 2157.
In Figure 32-50 on page 2158, Figure 32-51 on page 2158, and Figure 32-52 on page 2159 the second
LCDMCLK is shown as E1 and can be used as the enable strobe for a second display in Hitachi
mode. The primary enable strobe is the LCDAC signal.
Note: The acronyms WRSU, WRDUR, WRHOLD and GAP in the following figures correspond to the
bitfields of the LIDDCS0CFG register described in “LCD Interface Display Driver (LIDD
Mode)” on page 2156.
2157December 13, 2013
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TM4C129XNCZAD Microcontroller