Datasheet

32.21.1 LCD Interface Display Driver (LIDD Mode)
In LIDD mode, the LIDDCS0CFG register allows for full programmability of the read and write
strobes, data and enables. In the LCDCS0CFG register, the following parameters can be configured
with respect to the internal MCLK:
■ WRSU (bits[31:27]): Number of MCLK cycles that the LCDDATA bus, output enable, ADE, DIR
and CS0 signals have to be ready before the write strobe. The minimum value is 0x0.
■ WRDUR (bits[26:21]): Number of MCLK cycles for which the write strobe is held active when
performing a write access. The minimum value is 0x1.
■ WRHOLD (bits[20:17]): Number of MCLK cycles for which the LCDDATA bus, output enable, ALE,
DIR and CS0 signals are held after the write strobe is deasserted when performing a write access.
The minimum value is 0x1.
■ RDSU (bits[16:12]): When performing a read access, this field defines the number of MCLK cycles
that the LCDDATA bus, output enable, ALE, DIR and CS0 signals have to be ready before the
read strobe is asserted.
■ RDDUR (bits[11:6]): Number of MCLK cycles for which the read strobe is held active when
performing a read access. The minimum value is 0x1.
■ RDHOLD (bits[5:2]): Number of MCLK cycles for which the LCDDATA bus, output enable, ALE,
DIR and CS0 signals are held after the read strobe is deasserted when performing a read access.
The minimum value is 0x1.
■ GAP (bits[1:0]): Number of MCLK cycles (GAP + 1) between the end of one CS0 device access
and the start of another CS0 devices access unless the two accesses are both reads. In this
case, this delay is not incurred. The minimum value is 0x0.
Essentially, output valid/hold and input setup/hold times in LIDD mode are programmed by these
fields. In addition, the inherent clock delay from the internal MCLK transition to the signal output
adds or subtracts to these programmed times as indicated in the following tables and figures.
Table 32-67. LCD Switching Characteristics
UnitMaxNomMinParameter NameParameterParameter
No.
ns-50-Internal MCLK cycle timeT
CYC
L1
ns-25-Internal MCLK pulse duration highT
CYCH
L2
ns-25-Internal MCLK pulse duration lowT
CYCL
L3
ns11.6--Delay time from internal MCLK high to
LCDDATA[15:0] valid (write)
T
DLYVAL
L4
ns4.0--Delay time from internal MCLK high to
LCDDATA[15:0] invalid (write)
T
DLYINV
L5
ns11.19--Delay time, internal MCLK high to LCDACT
DLYHAC
L6
ns5.9--LCDAC transition timeT
TRANAC
L7
ns10.5--Delay time from internal MCLK high to LCDFPT
DLYFP
L8
ns5.9--LCDFP transition timeT
TRANFP
L9
ns11.0--Delay time internal MCLK high to LCDLPT
DLYLP
L10
ns5.9--LCDLP transition timeT
TRANLP
L11
December 13, 20132156
Texas Instruments-Advance Information
Electrical Characteristics