Datasheet

Figure 32-46. 100Base-TX Signal Detect Timing
N79
PMD Input Pair
Signal Detect
(Internal)
N80
Table 32-63. RMII Transmit Timing
UnitMaxNomMinParameter NameParameterParameter No.
MHz-50-EN0RREF_CLK frequencyF
REFCLK
N86
%60-40EN0RREF_CLK duty cycleDC
REFCLK
-
ns14-2EN0RREF_CLK to EN0TXDn,
EN0TXEN delay
T
TX_DLY
N87
Figure 32-47. RMII Transmit Timing
EN0REFCLK
EN0TXDn
EN0TXEN
Valid Data
N86
N87
Table 32-64. RMII Receive Timing
UnitMaxNomMinParameter NameParameterParameter No.
MHz-50-EN0RREF_CLK frequencyF
REFCLK
N91
%60-40EN0RREF_CLK duty cycleDC
REFCLK
-
ns--4EN0RXDn, EN0RXEN, EN0CRS setup
time to EN0RREF_CLK
T
RX_SU
N92
ns--2EN0RXDn, EN0RXEN, EN0CRS hold time
from EN0RREF_CLK
T
RX_HLD
N93
Figure 32-48. RMII Receive Timing
EN0REFCLK
EN0RXDn
EN0RXEN
EN0CRS
Valid Data
N91
N92 N93
2153December 13, 2013
Texas Instruments-Advance Information
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TM4C129XNCZAD Microcontroller