Datasheet

32.19.3 AC Characteristics
Table 32-53. Ethernet Controller Enable and Software Reset Timing
UnitMaxNomMinParameter NameParameterParameter No.
µs--45Time from the System Control enable of the
PHY to energy on the PMD output pin
ab
T
EN
N16
ns--110Time from software reset of the PHY to energy
on the PMD output pin
T
SWRST
N17
a. The PHY is enabled through System Control by setting the P0 bit in the PCEPHY register and the R0 bit in the RCGCPHY
register.
b. This minimum timing assumes the PHYHOLD bit in the EMACPC register is not set.
Figure 32-37. Reset Timing
CLK
N16
PMD Output Pair
PHY Enable
PHY SW Reset
N17
Table 32-54. MII Serial Management Timing
UnitMaxNomMinParameter NameParameterParameter No.
MHz2.5--EN0MDC frequencyF
MDC
N20
ns150-0EN0MDC to EN0MDIO (output) delay
time
T
MDIO_DLY
N21
ns--10EN0MDIO (input) to EN0MDC setup timeT
MDIO_SU
N22
ns--10EN0MDIO (input) to EN0MDC hold timeT
MDIO_HLD
N23
December 13, 20132148
Texas Instruments-Advance Information
Electrical Characteristics